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automatic test pattern generation

vead

Nov 27, 2011
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VLSI device are tested by automatic test equipment that perform verity of test
VLSI design are automated.
automatic test pattern generation is design automation process used to find test vector

I don't understand how the test vector generate automatically. can someone help ?
 

vead

Nov 27, 2011
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I think its software that generate test vector

ATPG tool like cadence

ATPG tools checks if the design is capable to perform the test according to the settings, then it generates test vector

according to statement software is used to determine test vector

I have done little work on cadence quartus software

I have written some verilog code for basic gates , flip flop

BUT I don't understand what is test vector that generate by software ?

someone can help me
 

Harald Kapp

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Nov 17, 2011
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A test vector is a set of input data to a circuit and the expected output data. It doesn't mattter whether the test vector is generated manually or automatically.
If the measured output deviates from the expected output, the circuit is faulty.
 

Harald Kapp

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by setting up input patterns and simulating the expected output pattern.
 

vead

Nov 27, 2011
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built in self test - ability of circuit to test itself
example memory bist, logic bist

scan technique used in design for testing
JTAG controller
full scan , partial scan

both scan and bist used additional test circuit for purpose of testing


I want to know how scan techniques are different from bist process
 
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