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Automatic Schematic Generation (System Graph) and Viewer

Discussion in 'Electronic Design' started by Alfonso Acosta, Jul 19, 2007.

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  1. Hi all,

    I'm developing a System Description Language (which could be used as
    an HDL in particular) called ForSyDe:

    I'm planning to add a backend to my compiler wich generates a
    graphical representation of the system.

    To my surprise, I havent found any tool which generates a schematic or
    system graph given a HDL model. Does anyone know any of them?

    Does any one know about a specific, open file format for schematics?
    My best options so far are GXL ( and GraphML
    ( but I coudn't find any free viewer
    with automatic routing support.

    Any help would be appreciated. Thanks in advance,

    Alfonso Acosta
  2. Clunixchit

    Clunixchit Guest

    Try the Alliance VLSI CAD, it is free and open source.

    One of its tools, boog can take a HDL model and generates a schematic
    which can be read with its xsch schematic viewer.

    PS: try it under a redhat or fedora based distribution or its clones.
    On a debian based distro, I had problems in installing alliance to be
    used with other commercial products.

  3. krw

    krw Guest

    Synplify Pro does (with HDL Analyst). It also generates bubble
    charts (something you might think about doing also).

  4. Shannon

    Shannon Guest

    Quartus II also has an RTL view and state-machine bubble viewer.
    ModelSim does as well. In fact, do any of the major tools NOT have a
    schematic viewer?

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