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Augh! WTF 'megabaud'?

Discussion in 'Electronic Basics' started by Rich Grise, Aug 6, 2005.

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  1. Rich Grise

    Rich Grise Guest

    OK, I guess it's almost OT for the crew, but, well, I was looking for a
    firm spec on Motorola's SPI bus. I've got a design going where I have to
    build one out of flip-flops and gates (Well, Xilinx does have shift
    register macros), but everybody who makes chips that use the SPI, has
    their own spec, it seems.

    So, I was going to ask, "Is there a definitive spec on SPI?" It's
    quite clear that the two (or more yada yada) devices have to have
    already agreed on a protocol. The thing is, I've been tasked to come
    up with the logic (that could be implemented in an FPGA or CPLD) that
    "does" an SPI. I think I'll either have a 24-bit register because one
    of the things that needs to be driven is a bank of 24 relays, or
    a 48-bit register because one of the things that needs to be driven
    is a DDS that takes a 32-bit command word.

    The point is, I haven't yet found a "SPI thingie" macro in Xilinx's
    schematics library - should I check their VHDL and Verilog libraries
    for such a thing?

    Failing that, is there a definitive spec that tells me how many
    nanoseconds are required as to the leading/trailing edges of CE,
    clk, etc, and are there any constraints as to the data frame?

    Oh, yeah, back to the topic: In my searches, this page came up:
    and if you scroll down to "SPI", in the third line of the first
    paragraph, the guy says:
    "...low/medium bandwidth (1 megabaud) network connection..."


  2. John Fields

    John Fields Guest

  3. John Larkin

    John Larkin Guest

    As far as I can tell, SPI means that there's a Clock line, a Data
    line, and a Strobe/ChipSelect somewhere nearby. Sometimes two data
    lines, in and out. I've seen "SPI" devices with bidirectional data,
    separate data, rising-edge clocks, falling-edge clocks, active-high
    select, active-low select, various logic levels, and all sorts of
    speed specs, up to 10's of MHz. If there are any rules, nobody seems
    to be following them.

  4. PeteS

    PeteS Guest

    You may be getting caught in the TLA duplication zone.

    The SPI you want is the 'Serial Peripheral Interface', originally by
    Motorola (now either Freescale or OnSemi, depending on your parts).
    There's a useful tools called SPIGEN at

    I have never found the definitive specification and simply used the
    timing diagrams from the 68332 family.

    There's a different 'SPI' physical layer that refers to the SPI-x
    System Packet level Interface (currently SPI4-2). You can read about
    that here:

    For SPI, (Mot style, anyway), you need MOSI (Master Out, Slave in),
    MISO, Clock.

    Some devices also need Frame / CS (the device becomes an active
    participant during frame active).

    Hope that helps


  5. PeteS

    PeteS Guest

    Rich said :

    As John stated, it could be :)

    I see your point though - Baud is perhaps the most misused term in
    communications I know of.


  6. John Larkin

    John Larkin Guest

    I love the 68332; I'm hacking a big assembly program right now.

    The only thing you can do when you use an SPI-claimed serial device is
    read the datasheet *very carefully*. Being lucky doesn't hurt, either.

  7. Bob Myers

    Bob Myers Guest

    Yeah, it's right up there with "bandwidth" (when used to
    mean "data rate" or "channel capacity") and "resolution"
    (when used to refer to the number of pixels an image
    or display provides in "X x Y" numbers)....

    Bob M.
  8. Wim Lewis

    Wim Lewis Guest

    Well, each symbol on the SPI data bus transfers 1 bit, so the baud rate
    and the bit rate of the bus will be the same :)

    Gotta agree with the stupidity of using "bandwidth" when "data rate" is
    meant tho'.
  9. Rich Grise

    Rich Grise Guest

    Touche`. :)


    Nah, just doesn't have the same 'Oomph!' to it. ;-P
  10. Rich Grise

    Rich Grise Guest

    LOL! Yeah, thanks for this. This is the conclusion I've been inexorably
    coming to - and I think that it doesn't even care if the clock is a
    nice, tidy, jitter-free pulse train - You put your zero on the CS,
    you put your data on MOSI, you put your one on "clock", you shift
    your data, lower the clock, count the bit, test, and if it isn't
    bit 8, shift and loop.
    Repeat for as many bytes as needed.

    It's even sounding like I could bitbang it raw, and it wouldn't
    matter if it got interrupted. The slave would just be sitting
    there, waiting for the next clock, until the next clock.

    [OBTW - the task has evolved to PIC, which it's turning out is
    also kewl - MPLAB is free! <leer, snort!>
  11. Rich Grise

    Rich Grise Guest

    Yeah, that's the one. :)
    Yes, and I've been doing just that, against the day that I find out that
    I have to make up my own spec for my own design, based on meeting all
    of the other chips' worst-case setup and hold times. I'm not too
    worried about clock rate, bitbanging. :)

    Other than that, I get the distinct impression (from my studies and
    feedback) that I can do pretty much any thing I want to. <leer, snort> >:->

    With a 4 MHz clock, a reasonably well-written loop could maybe do
    50 KBPS. That should be fine. :) GIVEN, of course, that I meet
    everybody else's setup and hold times, thresholds, and all that
    connect-the-dots stuff.
  12. John Larkin

    John Larkin Guest

    Just this afternoon we were discussing whether it was worth using the
    dedicated SPI interface in the 68332 to program a couple of Xilinx
    chips (essentially SPI in slave serial mode) or whether to just keep
    bit-banging like we usually do. We checked some old code and it looks
    like we're banging about 600 kbits/second, with a 20 MHz CPU clock. We
    copied (we call it "cached" to sound more professional) the code from
    eprom into CPU internal ram to speed things up, and the code is fairly
    tweaked assembly.

    We're planning a product with maybe 10 mbits of Xilinx configuration
    data, 15 seconds or so to configure, so the hardware SPI thing starts
    to look interesting there.

    Hey, if you had an fpga that was partially configurable, you could do
    a sort of bootstrap operation, serially load a small block that lets
    you parallel-load the rest.

  13. PeteS

    PeteS Guest

    Something I did not mention about 'SPI' is that it's sometimes called a
    Sync Serial Interface, and there are 3 variants at least:

    Intel Style (single data line that gets turned around, but still uses
    the same overall protocol)
    National (almost like Mot)
    Mot style.

    Take a look at this datasheet

    It's a device I'm using in a design and around page 20 or so you get a
    choice of interface styles on the sync serial (command) port.


  14. Rich Grise

    Rich Grise Guest

    Thanks for this. I'm definitely feeling a lot more comfortable about
    just saying, "This is how my design outputs its SPI, and BTW here
    are the command strings it's going to be expecting from your Master
    Control Computer." I guess if I'm the designer, that is my job,
    after all. :)

    Thanks again!
  15. Rich Grise

    Rich Grise Guest

    Well, I've still got custody of my client's Xilinx development board,
    but the project has gone micro - PIC16F627A, and I've downloaded MPLAB,
    which is also way cool.

    But I look at that Xilinx IDE, and all of the libraries, and I salivate.
    You can do _ANYTHING_ with that chip! The development board ships with
    an 8-bit Johnson Counter already programmed into it. Chasing LEDs don't
    photograph well. :)
    file:/home/richgrise/Pictures/100_fuji/dscf0307.jpg - no flash
    file:/home/richgrise/Pictures/100_fuji/dscf0308.jpg - with flash; you
    can just barely tell that the four lower LEDs are lit. :)

  16. John Larkin

    John Larkin Guest

    Exactly. We don't follow rules, we make rules.

  17. PeteS

    PeteS Guest

    I still have the full Xilinx ISE system on my computer, with all the
    libs. I had to do a major interface design and you're right - you can
    do *anything* with the things.

    That beast had to interface from **6** PPC busses (although I had two
    busses per port as I had CS0/1 functionality on the targets) to a
    single synchronous bus and provide data / message buffering per
    channel, a priority interrupt controller and message handling by
    message type.

    I love the Xilinx implementation of dual port RAMs - clean and easy to
    use. I must admit the internal address decoder was a large chunk of
    Verilog, to say nothing of the 7 picoblaze cores I instantiated ;)

    The only problem I have had with FPGAs is cost - it has to replace a
    fairly major piece of hardware to be cost-effective (although playing
    Altera against Xilinx has been known to bring the proce down :> )


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