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ATX PSU Power Toggle Circuit

markdixon

Oct 15, 2014
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Hi all, I am designing a project that I want to run off an ATX PSU and I wanted to use a push button for the On/Off mechanism, just like a desktop PC.
I have uploaded a design for a circuit in Eagle (lite) which I think will work. It uses the +5v standby voltage the ATX PSU provides to power a J-K flip flop (POWERA on the schematic) (schematic stolen from Instructables here), which I have linked to a transistor which then pumps the +5v standby into the ATX PSU's Power On signal line.
So far the design is purely schematic, I haven't tried wiring it up or any testing, I don't really have the parts as yet, I just want to know if it looks legit.
Also, unless I've misread on how the flip-flop works, am I right in thinking that the two outputs Q/!Q will toggle between one and the other when S1 is pressed, effectively showing my 'Standby' and 'On' LED's?
Ignore the USB bit... the end goal for this is to power a RasPi with some other bits and pieces in a 2U rack mount enclosure where I can toggle and monitor several mains (IEC) sockets to manage a load of Cisco routers/switches.

I know I need some proper values for the transistor and some of the resistors but it was just to get me started.
1st Power Control circuit.png
Let me know what you think.

Thanks
 

Arouse1973

Adam
Dec 18, 2013
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Hi Mark
The Flip-Flop looks ok to me. The green LED might be a problem though because it won't have enough voltage across it when the transistor switches. You can connect this with it's resistor across the output you are switching. Or connect it across the output of the flip flop and then feed the base of the transistor from the flip flop with no resistor because you are using it as an emitter follower. Also don't forget some capacitors across the supply for decoupling and support.
Adam

FLIP FLOP.JPG
 

hevans1944

Hop - AC8NS
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I think you should de-bounce and clean up the rise and fall times of the signal applied by S1 to the CLK input of the 4027. Otherwise, you may get multiple "clock" pulses each time the switch is actuated and then deactuated to create a positive-going clock. If this occurs, each of the extra pulses will change the state of the output.

Switch bounce means the contacts of an open switch do not close and stay closed: there is a bounce to the contacts that causes them to briefly open, then close, then open, then close until the contacts finally settle down in the closed state. How many bounces occur depends on the switch construction. In your circuit, if bounce occurs when the switch is pressed (closing the contacts), then each bounce creates a positive-going pulse that may clock the flip-flop. When the switch is released to open the contacts (and intentionally clock the flip-flop) bounce is less likely to be an effect of the contacts opening.

Unless the clock input to a flip-flop is specified to be level triggered, not edge triggered like the 4027 is, interfaces to the real world of bouncy switches and other things that go bumpity bump in the night should always have their state transitions conditioned to conform with the rise and fall times of whatever logic family they intend to drive. For the 4027 CMOS J-K flip-flop, clock transitions must be no longer than 15 μs for a 5 V supply. One, and only one, logic transition from a properly conditioned switch will occur each time it is actuated or de-actuated. The rise (or fall) time depends on the logic family used to condition the switch.
 
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Arouse1973

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I think you need to de-bounce and clean up the rise and fall times of the signal applied by S1 to the CLK input of the 4027. Otherwise, you are likely to get multiple "clock" pulses each time the switch is actuated, each pulse changing the state of the output.

Unless the clock input to a flip-flop is specified to be level triggered, not edge triggered like the 4027 is, interfaces to the real world of bouncy switches and other things that go bumpity bump in the night should always have their state transitions conditioned to conform with the rise and fall times of whatever logic family they intend to drive. For the 4027 CMOS J-K flip-flop, state transitions must be no longer than 15 μs for a 5 V supply. A single switch actuation will result in one and only one logic transition from a properly conditioned switch. The rise (or fall) time will depend on the logic family used to condition the switch.

Good point , I missed that one.
Adam
 

hevans1944

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Jun 21, 2012
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My advice above was from many years experience interfacing real world devices with TTL circuits. TTL is pretty much unforgiving when it comes to enforcing rise/fall times, setup/hold times, and logic levels. Schmitt-trigger inverters, when they became available as TTL components, were a God-send.

Sometimes switch bounce doesn't make any difference, for example, if whatever the circuit is responding to occurs on the first contact closure and further opening and closing of the contacts is ignored. The classic two-NAND flip-flop switch conditioner described below is a good example.

For TTL switch input signal conditioning, I almost always specified a SPDT switch and connected each of the stationary contacts to one input of a pair of 2-IN NAND gates with 1 kΩ pull-up resistors to Vcc on each switch contact input. The switch common (moving contact) goes to ground. The other two inputs of the two NAND gates are cross-connected to the NAND outputs, thus forming an R-S latch that is set or reset by the switch position. Transition from set to reset, or from reset to set, occurs on the first contact closure and further bounce transitions are ignored. This circuit also works well with two normally-open push-button switches if both switches are not pressed at the same time.

Another old TTL "trick" is to wire up a pair of inverters as a flip-flop, output of one inverter connected to input of the other and the output of that one connected back to the input of the first. Connect the SPDT switch contacts to each of the inverter outputs and the switch common to ground. If the output of the inverter that has it's output shorted to ground by the switch was originally high, it doesn't stay that way for long. Its low-level short, presented as an input to the other inverter, drives the other inverter output high which then asserts a low output from the inverter whose output is shorted to ground by the switch. All this happens within nanoseconds during power-up or if the switch changes states, regardless of any bounce that may be occurring. There were years of debate in the trade literature regarding the validity of this two-inverter switch de-bouncer, so please don't revive that here. It works, and I have never had an inverter fail because of alleged stresses during switching. Besides being simpler, no pull-up resistors are required. What's not to like? Still scared? Use open-collector inverters with 1 kΩ pull-up resistors.

73 de AC8NS
Hop
 

KrisBlueNZ

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Hi Mark and welcome to Electronics Point :)

Your basic idea is good, but there are a few problems with that design.

As Hop pointed out, you need to debounce the pushbutton. Mechanical switches and pushbuttons suffer from a problem called contact bounce, which you should Google. (Edit: Actually, Hop described it pretty well in post #3.) There are various ways to debounce a pushbutton; generally they involve converting the pushbutton state into a voltage (using a pullup or pulldown resistor), feeding that voltage through a resistor into a capacitor to produce a slight delay and a smoothing effect, and feeding that voltage into a Schmitt trigger. Alternatively if you can find a SPDT pushbutton, you can use the other half of the 4027 to debounce it, by connecting the NO and NC contacts to the S and R inputs. (Edit: This is the same idea that Hop described in post #5 but you can use the other half of the 4027 instead of two NAND or NOR gates.)

Also as Adam pointed out in post #2, you need a decoupling capacitor across the supply pins of the 4027. Normally a 0.1 µF ceramic is used.

The third problem is that the ATX PS_ON signal is actually -PS_ON; it's activated by pulling it low, not pulling it high. In other words, it's an active low signal that needs to be pulled down to 0V. You can do this using an NPN with its emitter connected to 0V with its base connected through a current limiting resistor (and optionally also through an LED) to the flip-flop output that goes high when you want the power supply to run. When that output goes high, current will flow through the resistor, through the LED if present, and into the base of the transistor, turning it ON and making it conduct from its collector to its emitter, pulling -PS_ON low and making the main power converter start up.

In your circuit, R4 at 250 kΩ won't allow enough current to light the LED. Assuming you connect the LED and series resistor between the flip-flop output and the base of the transistor that drives -PS_ON, the resistor should be about 470Ω. This will result in an LED current of about 4 mA, and you shouldn't really try to draw more than that from a CMOS 4000-series device output, especially at a supply voltage of only 5V. You could use transistors to drive the LEDs if you need more current than that, or you could use high-efficiency LEDs.

R2 and R5 at 4k7 will also not produce much illumination in their LEDs. Do you know how to calculate the LED current given the supply voltage, the forward voltage of the LED, and the resistance of the series resistor? See Steve's tutorial at https://www.electronicspoint.com/resources/got-a-question-about-driving-leds.5/.

R3 isn't needed; you can connect the J and K inputs of a 4027 directly to the VDD pin.

Re the connections to pins 4 and 7 of the 4027. It's perfectly fine to cross wires over each other. Wires on a schematic are not like tracks on a circuit board; they won't short together if they cross each other. There's no need to route that line all the way round the outside of that circuit block!
 
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hevans1944

Hop - AC8NS
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Good post, as usual, Kris. I didn't notice that -PS_ON was active-low.

On schematic construction: wires that cross are assumed to not be connected, as you stated. Placing a dot where three wires connect is preferred practice. Avoid placing a dot where two wires cross and the intent is to connect. Break one of the two wires into two, one above and one below the second wire. Offset one of these "broken" wires to one side and place two dots. I sure wish I had my schematic capture program up and running to illustrate this. Does anyone remember when the "little tunnel" construct vanished? This was a little semi-circle inserted in a wire, intended to show that two wires crossed but didn't connect. It really cluttered up a complex schematic.
 

KrisBlueNZ

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Perfect, Hop. I'm working on a "KrisBlueNZ's recommendation for connected and crossing wires for clear schematics" now. There are quite a few options, but only a few that are unambiguous.
 

KrisBlueNZ

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Here are my recommendations for how connected and unconnected wires should be shown on schematics for maximum clarity and minimum ambiguity.

KrisBlueNZ's wire junctions and crossings recommendations.png
My reasoning:
  • (a) is unacceptable because junctions should always have dots.
  • (b) is unacceptable because it may be hard to distinguish from (m) if the image is resized, or printed and photocopied.
  • (c) is acceptable but may be better avoided because it looks a bit odd! You could move components slightly and use (e) instead.
  • (d)~(f) are preferred because (i) all junctions have dots; (ii) if dots are not clear, it's impossible to confuse them with unconnected lines; (iii) there are no 45° lines.
  • (g)~(k) add unnecessary visual clutter, especially when many lines cross many other lines.
Comments?
 
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Arouse1973

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The other reason (b) should not be used IMO is because of the quality of some photo copiers the first thing that used to fade after repeated copies of copies were the dots. This sometimes lead you to thinking it wasn't connected.

Adam
 

KrisBlueNZ

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Thanks Adam. That was what I meant. Although photocopying isn't used much nowadays! But I've clarified the reason in my description.
 

markdixon

Oct 15, 2014
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Thank you everyone for your comments.
I did know about a few issues in the diagram but I can't believe I missed the PS_ON being active low!
I got myself in a bit of a mess over debouncing the input from S1 as I've seen the problems it causes using microcontrollers and reading a digital pin connected to a tact switch, and even seen it on a scope, but because the original circuit I borrowed the design from didn't have it and seemed to work ok I didn't include it, and came to the conclusion that the 4027 had internal caps to do it for you, then realised why would it do that when you can drive the trigger from other sources and not just a tact switch! argh.
I also realised after posting that the Green PON LED was in the wrong place and I was going to redo it as @Arouse1973 second example (as in my newbie mind that makes more sense to me than the first one).
As for overlapping wires in my diagram that aren't connected, just a little bit of OCD from me :)
I knew about working out the resistor values for the LED's etc but just filled it with random values because I wanted to run the ERC/DRC in Eagle and get rid of any warnings.. again, a bit of OCD.

@hevans1944 I remember seeing that little hump-bridge looking symbol reading old Haynes Car manuals! Didn't realise it was now a defunct symbol!

When I get chance I will correct as much as I can and also add more bits to the design.
PS. Expect a seperate post on relays, SSR's and such shortly ;)
 
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markdixon

Oct 15, 2014
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Hi again,
I have reworked my design and watched a very good tutorial on Youtube for using a Schmitt for the output. Here's my redesigned circuit
2nd Power Control circuit.png
I decided to drop the power on LED because it wasn't needed. There will be other indicators that the power is on!

Again, let me know what you think. I have put some values in the LED's and resistors so should be a little more comprehensive now.

Thanks
 

KrisBlueNZ

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I'd use 10k resistors for R3 and R4, as well as R1, just to shorten the BOM. And to save a bit of current, in the case of R4. You don't need to provide much base current to Q1; it is not driving a heavy load.

That allows you to reduce C2 to 1 µF or less (0.47 µF for example), so you could use an MLCC (multi-layer ceramic capacitor) instead of an electrolytic or tantalum capacitor.

The STANDBY LED you have connected to the -Q output of the flip-flop will actually light when the power supply is ON, not when it's in standby.

I think I mentioned this already: you can avoid the 74HCT14 if you use an SPDT pushbutton and feed the NC and NO contacts into the S and R inputs of the other flip-flop in the 4027. The idea is the same as shown here (the two NAND gates form an SR latch) except you need to exchange VCC and 0V because the inputs to a NAND gate SR latch are active low, whereas the 4027's S and R inputs are active high.

e8nrL.jpg

(Image from: http://electronics.stackexchange.co...h-debouncing-would-toggle-switch-still-bounce)
 

markdixon

Oct 15, 2014
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@KrisBlueNZ Thanks for all the input you've given me.
I think I need to go back to the drawing board on that STANDBY LED; I was told the two outputs on the 4027 were called Q and !Q (not Q), with !Q being active low, meaning that when Q was high, the output of !Q would be high and LED would be off, when Q was low, !Q would be low so the LED would be on.
More reading!
Thanks all.

[edit] The more I read that the more it sounds stupid. I can think of other ways to implement this so will look into it.

Thanks
 
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KrisBlueNZ

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Yes, the Q and -Q (aka Q-bar) outputs are always in opposite states.

The power supply is fully enabled when Q1 is conducting, which corresponds to positive voltage through R4, which corresponds to the Q output being high. At that time, the -Q output will be low, and you've connected the STANDBY LED between the 5VSTANDBY rail and -Q, so it will illuminate when -Q is low. So the STANDBY LED will illuminate when the power supply is fully enabled, which is the opposite of what you want.

You just need to reverse the direction of the STANDBY LED and return R5 to the 0V rail instead of 5VSTANDBY.

These references relate to the schematic in post #13.
 

markdixon

Oct 15, 2014
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@KrisBlueNZ Thank you once again!
To stop me getting more and more confused, I have found a SPDT pushbutton that I can use as my power button, can you show me or direct me to an example using the second inputs on the 4027 to debounce the button? I understand the logic behind the two NAND gate system but dont know how this relates to the 4027.
Thanks
 

markdixon

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@KrisBlueNZ I feel like I'm bordering on annoying here, but I studied your diagram and thought "but surely that's just going to go immediately back to low on the output Q when I release the button?"
Then looked back over the previous posts and you mention using the other flipflop of the 4027. So I take the output from Q which is now debounced and put that in place of my pushbutton on my original diagram?
Thanks
 
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