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Attn Fred Bloggs I have redesigned my Binford 7000 light controller

Discussion in 'Electronic Basics' started by Scott Wiper, Apr 1, 2004.

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  1. Scott Wiper

    Scott Wiper Guest

    As you can see in these images.

    Sheet One.

    On this shhet I am still using the 2.45760MHZ clock osc. U1.

    U3 That is marcked as "U" is my 60HZ duty cycle at 50%. This is used t time the 273 as a ADC.

    U7 first ouput PIN 1 from the LDR is or gated to the master reset. and so is the power on reset.

    U4 and U5 is a 120 count duty cyle I hope taking into the fact that binary is base 2 1/0
    This should give me a main 1HZ as indicated.

    U5 and U6 are paired to together for a 120 count X2 should give me a 30 minute duty cycle.

    I took your advice and ored the Master Reset and the Delay 4017 together to remove the randomness from the five hour delay. Everything comes out reset at the same time when the LDR is below it's set point. The 74LS21 Can and will be replaced with 4082 gate.

    Sheet Two.

    Uses the main frequency of 2.45760 MHZ to advance my electromachinical totaliser. Through Q1. D5 sould be in parallel with the EM totalser. I will correct this and you will see the change. The 74LS21 is being replaced with a 4082 gate.

    Sheet Three.

    Is ment to drive the solid state realys and some panel LEDs. They are as reverced Express PCB is well aware of this they are patching the problem. I will be putting low current incandesant panel lights in parallel with the solid state relays +/- controll pins to make blink light up and flash even more.

    PS. I don't why this is everything a man sees has to blink light up and flash even when we build it. Weman. just stand their shanking their heads saying "That's nice dear... It's got pretty lights dear."
  2. Fred Bloggs

    Fred Bloggs Guest

    Maybe a slight arithmetic error here: U2 Q14 outputs
    2.457600MHz/(2^14)=150Hz, the 4017 Cout divides by 10 for 15Hz and not
    60Hz. Then the RLY A DRV holds all the counters in reset so that U8
    LS273 loses its CLK and can no longer sample the LDR comparator output-
    the circuit is frozen. The RLY A DRV should only reset U6 and U9, and
    allow the 1Hz clock counters to free run to free-run. And since U13 on
    sheet B produces a clean 1Hz, this should be used on the sheet A for the
    "main 1Hz" and eliminate the 1Hz counters on sheet A.

    That circuit is excellent! It should work great-
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