Connect with us

Astable Multivibrator Generates Sub-Ground Voltages

Discussion in 'Electronic Basics' started by Jeff, Nov 5, 2005.

Scroll to continue with content
  1. Jeff

    Jeff Guest

    Hello,

    I've been simulating a circuit of the 'classic' astable multivibrator
    and analysing the results. This is the old-fashioned two-transistor
    design where each device (both NPNs) alternately turns off/on the
    other. I'm sure you know the type of thing. Anyway, the collector
    voltage of Q2 goes negative to almost the extent of the supply rail! Is
    this a Spice anomaly or would a real world circuit do the same? I don't
    see how it's possible for a circuit to generate sub-ground voltage
    levels. Isn't that theoretically impossible? The clock rate is 400Hz
    and Vcc is 5V.

    -Jeff.
     
  2. Jim Thompson

    Jim Thompson Guest

    Which "Spice"? Can you post a schematic, either ASCII, or a real
    schematic (preferred) to alt.binaries.schematics.electronic ?

    ...Jim Thompson
     
  3. Jeff,
    I wouldn't expect the collectors to go beyond the supply
    rails, but the bases will go negative. Since the B-E
    breakdown isn't usually modeled in SPICE, this can give
    some un-realistic waveforms in simulations.

    --Mike
     
  4. Jeff

    Jeff Guest

    Hi and thanks.
    I've just double-checked the simulation and it's actually the *bases*
    of both devices that go negative to -4.3V rather than the collectors,
    so my apologies. But the question still remains about how *any* node in
    such a circuit can go below GND. I will post the schematic if the above
    correction still doesn't account for what I'm seeing.
    -J.
     
  5. Jeff

    Jeff Guest

    Hi and thanks.
    Yes, it's the bases that are going negative. I'm not sure why you
    mention "breakdown voltages" since we're only talking about a Vcc of 5V
    and I know of no transistor that breaks down at such a low reverse
    Vbe., nor why a spice model should fail to take account of it if such
    should be the case. It seems like a pretty significant flaw in the
    model if so.
    BTW, in answer to Mr. Thompson's question, I'm using LT Spice.
     
  6. Jeff,

    It probably won't breakdown at 5V. But it might around 6. Usually
    transistor breakdown isn't modeled because the normal design flow
    is to simulate to find what the peak voltages are and then buy/fab
    a transistor that won't breakdown in the circuit. If the transistor
    breaks down in simulation, then you don't know what kind of transistor
    you need to buy/fab. Transistors usually aren't used in a manner that
    includes breakdown, because that has a permanent effect on the device
    (though the effect from B-E breakdown is not too dramatic). But
    basically, if you simulate with transistors that breakdown in simulation,
    you might want to think for a second and make sure your not designing
    the circuit to fail.
    LTspice comes with an example astable circuit typically installed
    as C:\Program Files\LTC\SwCADIII\examples\Educational\astable.asc

    --Mike
     
  7. Jeff

    Jeff Guest

    Okay, thanks for that.
    So it appears it's either a model deficiency or real-world capacitive
    effect. I need to know which, so here's the netlist of the circuit
    concerned and I invite comments on it:

    "ExpressPCB Netlist"
    "SwCAD III Version 2.16i"
    1
    0
    0
    ""
    ""
    ""
    "Part IDs Table"
    "Q1" "2N3904" ""
    "Q2" "2N3904" ""
    "V1" "5" ""
    "R1" "1k" ""
    "R2" "1k" ""
    "R3" "15k" ""
    "R4" "15k" ""
    "C2" ".1µ" ""
    "C3" ".1µ" ""
    "R5" "100k" ""

    "Net Names Table"
    "N005" 1
    "N003" 5
    "0" 8
    "N002" 12
    "N004" 15
    "N001" 18

    "Net Connections Table"
    1 1 1 2
    1 5 2 3
    1 9 1 4
    1 10 1 0
    2 1 2 6
    2 6 2 7
    2 8 1 0
    3 1 3 9
    3 2 3 10
    3 3 2 11
    3 10 2 0
    4 2 1 13
    4 4 2 14
    4 8 2 0
    5 2 2 16
    5 7 2 17
    5 9 2 0
    6 3 1 19
    6 4 1 20
    6 5 1 21
    6 6 1 22
    6 7 1 0
     
  8. Tim Williams

    Tim Williams Guest

    Which reminds me, I've ran such a circuit at 18V before with no
    problems. .

    Tim
     
  9. none

    none Guest

    When you capacitively couple two stages, the coupling capacitor will
    charge up to the power supply minus the base voltage. When the
    transistor collector goes to ground, you now have a charged capacitor
    whose positive end is near zero volts. Thus the other end will be
    nearly the supply voltage below ground. The capacitor will then
    discharge and charge up in the other direction to the difference of
    the collector saturation voltage and the base voltage.
     
  10. Jim Thompson

    Jim Thompson Guest

    Capacitive coupling?

    ...Jim Thompson
     
  11. Jamie

    Jamie Guest

    i guess that would depend on where the test points are?
    you maybe getting a - reading but maybe your testpoints
    are between to area's that are reverting the polarity ?
    the only other thing i could think of is that you
    are not testing with DC but maybe via a cap that could
    generate - voltages.
     
  12. Jamie

    Jamie Guest

    sounds like the Cap Discharge effect.
     
  13. Jasen Betts

    Jasen Betts Guest

    ["Followup-To:" header set to sci.electronics.cad.]
    That's normal and does happen in the real world.


    The culpret is the capacitor attached to the base, when Q1 switches on
    the other end of the capacitor does from somewhere close to the supply
    voltage down to near gound, this voltage change is mirrored at the other
    end of the capacitor pushing the Q2 base below ground.


    Bye.
    Jasen
     
  14. Fred Abse

    Fred Abse Guest

    Consider the circuit below:




    o------o------. +V
    |
    |
    |
    | o
    S1 |=|>
    | o
    |
    ----------o------------
    | | |
    | | |
    | .-. |
    | | | |
    | | |R1 |
    | '-' |
    | | |
    | | |
    | | o |
    .-. | |=| S2
    | | | o |
    | |R2 --- |
    '-' --- C |
    | | |
    | | |
    '---------o |
    | |
    | |
    V D |
    - |
    | |
    o--------------o-----------o--. 0V


    R2 >> R1

    Close S1 until C has charged to +V, minus the forward drop of D


    Open S1 and close S2


    C cannot discharge instantly, only at a rate set by C(R1+R2). Its upper
    terminal is now connected to 0V, hence its lower terminal must be negative
    wrt 0V. D is now reverse biased.

    We now have a decaying negative voltage at the junction of C and D anode.
    The rate of decay is set by C(R1+R2)


    That's how you get nodes going below 0V
     
  15. kell

    kell Guest

    It's real.
    Stop thinking about your simulator for a minute.
    If you look at an astable multivibrator and analyze it, you
    will see.
    You have a charged capacitor and suddenly you pull the high
    end of the capacitor to ground.
    Well, obviously the low end of the capacitor will go to a potential
    that's negative with respect to what you are considering "ground,"
    which by the way is only a reference, not a barrier.
    You could analyze the circuit with a positive "ground" at Vcc,
    all the potentials would be negative with respect to that.
    I suspect that it wouldn't bother you that the negative terminal
    of the cap flies up and down, since it never crosses Vcc "ground"
    in doing so.
     
  16. Jeffers

    Jeffers Guest

    Okay, Fred and Kell. Some really eye-opening and helpful ways of
    re-examining the 'problem' (such as it was) for which I'm most
    appreciative.
    Thanks!
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-