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ASIC costs

K

Ken Smith

Jan 1, 1970
0
Joerg said:
If somebody wanted it really bad they'd figure out the functions and
precision and just hire a good analog engineer to design the innards
from scratch. It will cause a delay but probably not much more than
grinding off the part numbers in your current design would.

I've had to figure out the circuit from something with removed numbers.
It took me about an hour. BTW: I was repairing something.


The fun thing about the ASCI is that they have to run signals in and look
at the output. If things are a non-linear function of the past, figuring
out what a circuit does can be tricky. Think about characterizing an AGC
system. It is a lot harder than a simple filter.

Sometimes a DSP solution can be harder to crack than an ASIC. Especially
if it contains nifty algorithms that run internally and where the code
can't be read back out.

The problem with the FPGA idea is that the boot up stuff is not stored
right in the chip so it is very insecure. I don't know of a normal DSP
that doesn't also have this problem. A DSPic may be the answer for some
of the circuit.
 
T

Tim Hubberstey

Jan 1, 1970
0
Ken said:
The problem with the FPGA idea is that the boot up stuff is not stored
right in the chip so it is very insecure.

Xilinx has addressed the security issue in some of their parts by
providing a small area of battery-backed write-only RAM where decryption
keys are stored before the product is shipped. At each boot, the
bitstream is downloaded in encrypted form and decrypted by a built-in
decryption engine in the chip.
 
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