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ASIC costs

Discussion in 'Electronic Design' started by Ken Smith, Feb 2, 2005.

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  1. Ken Smith

    Ken Smith Guest

    Imagine that you have a circuit involving about fast 8 op-amps (LT1224), a
    couple of fast comparitors (LT1016), about 10 discrete transistors and
    about 8 polse of filtering. How much are we talking to make an ASIC out
    this.

    If we also have about 500 macrocells worth of CPLD, an 8051 or so and
    about 4Meg of fast RAM. All this runs at about 100MHz. Is it cheaper to
    make one ASIC or two.
     
  2. Presuming a lot of things:

    Solution 1: No ASIC: Put the embedded micro, 500 macrocells into an
    FPGA. Get rid of (almost) all the analog ... put that in the FPGA too
    .... digital filtering. Memory ... if you can use SDRAM, leave it
    outside ... $1.25 to $2.00. Total cost < 10.00 + ADC.

    What does it do? More information please. The mask set for a large
    mixed signal ASIC (0.35 micron) can cost about $275K. The engineering
    NRE ... depends. How many?

    Solution 2: you can include a fast ADC and the DSP stuff in the ASIC
    above, no need for the fpga. 4Meg of ram is a lot to include, though
    .... will probably still be cheaper outside. ASIC Total cost (SWAG)
    $5.50 each @ 250K pcs / yr. Not including NRE and mask fees.

    Just my own opinion.

    Frank Raffaeli
    http://www.aomwireless.com/
     
  3. Have you looked at the programmable analog parts from Cypress and Zetex ?
     
  4. Do the comparators work faster than the clock ?
    Is the filter faster than the clock ?
    Do you need more dynamic range than say 8 bits ?

    Rene
     
  5. Ken Smith

    Ken Smith Guest

    This is more or less the direction I've intended but I want to compare it
    with others. Converting the analog to digital is a bit of a problem. The
    extra prop. delay could be serious trouble for part of the system.
    I could tell you but then I'd have to kill you. It is a secret that I
    really-really don't want to give away.
    Not as many as you may think the ASIC is going to be expensive on a per
    unit basis, but other solutions are expensive too.
     
  6. Ken Smith

    Ken Smith Guest

    Yes but they don't look to be exactly what we need. They may be part of a
    multiple chip solution though.
     
  7. Ken Smith

    Ken Smith Guest

    Do the comparators work faster than the clock ?[/QUOTE]

    The delay through one of them must vary by less than 4nS.

    I can't stand any cogging in the comparitor so it must not be synced to
    the clock edge unless the clock is very high. (About 10GHz)
    Yes as things stand it is.
    Yes, at least 16 bits looks to be needed. It may be more depending on how
    the quantization interacts with the rest of the system.
     
  8. Joerg

    Joerg Guest

    Hello Ken,

    Consider Frank's ADC-DSP idea but use a fast and modern DSP with plenty
    of floating point horsepower, multiplier, leather seats and the whole
    nine yards. No FPGA. It might be able to do the filtering and stuff at
    an acceptable prop delay penalty. For cost reasons 4MB RAM might better
    be kept outside as an extra chip, at least for the time being.

    Regards, Joerg
     
  9. Ken Smith

    Ken Smith Guest

    I think this is coming down to the "find another way" result. It looks
    like the ASIC is out of the question. Maintaining an input to output
    delay that is stable with a DSP sounds tricky (hmmmm unless).

    There can't be any beat between the harmonics of the input and the clock
    of the DSP. None = less than 0.0001 degrees RMS of phase jitter in a
    500KHz signal. A fixed phase error can be about a degree without too much
    trouble.
     
  10. You can get an idea of the costs by checking the MPW prototyping
    prices at www.mosis.org or www.europractice.imec.be depending on
    at which continent you reside. At larger quantities the per-chip costs
    are less. The direct links to the price lists are

    http://www.mosis.org/Orders/Prices/price-list-domestic.html
    http://www.europractice.imec.be/europractice/on-line-docs/prototyping/sp/protprices2005.html

    One more site is http://cmp.imag.fr , but being french it may cause
    blisters to a certain fraction of US-based engineers.

    The numbers in the above sites are fabrication only; you'll have to
    reserve some amount for layout and simulation; also for purchasing the
    IP blocks for the 8051 and opamps if you don't want to design them
    transistor-by-transistor. This may end up to be a larger sum than
    the fabrication cost. An example:

    http://www.austriamicrosystems.com/05foundry/ip_start.htm

    The readily-available blocks are no LT1224's either; you may have to
    do some searching to find suitable amp blocks. 8051's are often
    available as synthesizable cores for most mixed-signal processes.

    I seem to recall that at some time some foundries used to offer
    some IP blocks as "GDS black boxes" for free. You would just add
    a black box with a predetermined size and contact locations on your
    layout and the foundry would fill the boxes with transistors etc.
    at the fabrication time. This way the foundries were able to make
    their bread out of the fabrication fees alone. But this may no longer
    be true in the greedy modern times.

    Regards,
    Mikko
     
  11. Tim Shoppa

    Tim Shoppa Guest

    None = less than 0.0001 degrees RMS of phase jitter in a
    500KHz signal.

    That corresponds to 0.55 picoseconds. That's achievable in at least
    some domains, but not knowing the real need it's starting to sound like
    specsmanship.

    Tim.
     
  12. Joerg

    Joerg Guest

    Hello Tim,
    Plus exactly determining the number of clock cycles it takes to execute.
    Should be possible even on newer DSP. We have done that but it was with
    the old Analog Devices 2105 processors. These may look like a moped
    compared to today's rocket DSPs but one single clock cycle of skew would
    have thrown our whole Doppler detection off kilter. It didn't, operated
    like clockwork.

    Regards, Joerg
     
  13. Ken Smith

    Ken Smith Guest

    Remember that this is an RMS jitter (ie: short term) not the absolute
    error of the long term drift. The 0.0001 degrees number comes from the
    real requirements to match the system performance.

    Now: what does "some domains" mean in this context.
     
  14. Ken Smith

    Ken Smith Guest


    Imagine you have a signal at 500.001KHz and you digitize it at 5MHz. When
    you digitize, you add distortion products and these will beat with the
    5MHz and the waveforms slide past each other. When you are done with the
    DSPing, you are going to turn the signal back into analog. At this point
    more distortion products get added.
     
  15. Ken Smith

    Ken Smith Guest

    I can convert from 8051 to equivelent logic.
     
  16. Tim Shoppa

    Tim Shoppa Guest

    Now: what does "some domains" mean in this context.

    0.55 picoseconds is a pretty good jitter figure for leading-edge
    technology telecom clocks. Typical rise and fall times for these
    pulses is of the order a few tens of picoseconds. Trying to do the
    same thing for a sine-shaped wave of 500kHz (which is a fall time of
    millions of picoseconds) is ludicrous. The noise on your noise on your
    noise will make this impossible.

    Tim.
     
  17. Joerg

    Joerg Guest

    Hello Ken,
    You'll need all the ADC bits money can buy. 16 bits would be possible at
    5MSPS but it'll be expensive, probably above $30 plus lots of housekeeping.

    Question: Why do you want to integrate this anyway? Space constraints?
    Cost?

    Regards, Joerg
     
  18. Ken Smith

    Ken Smith Guest

    $1000 each would not kill the idea. That would still make the ASIC less
    than 25% of the total cost of the current system. A lower price would be
    nicer.
    This is one part of it.
    This is not really an issue with the electronics a things stand.

    Another reason is to help keep what we are doing a secret. I figure it
    will delay the other guys by more than a year. A small time operator
    won't have the ability to copy an ASIC.
     
  19. Ken Smith

    Ken Smith Guest

    The current system involving op-amps and comparitors and stuff works.
    This means that in the band of interest[1] the RMS phase jitter is under
    0.0002 degrees. Yes it is at the high end of what crystal oscillators
    will do[2]. I'm paying $350 for my oscillators. Some of the specs for
    the oscillator are much tighter than the specs of the telcom ones.

    [1] 0.001Hz to 1KHz from the "carrier" matters most

    [2] OCXOs will do it, TCXOs will not.
     
  20. Joerg

    Joerg Guest

    Hi Ken,
    Ah, nice. I am usually at the other end of the spectrum, turning every
    dime a dozen times. Believe it or not, that is med electronics which
    used to be like your stuff where only performance mattered. Not anymore.
    If somebody wanted it really bad they'd figure out the functions and
    precision and just hire a good analog engineer to design the innards
    from scratch. It will cause a delay but probably not much more than
    grinding off the part numbers in your current design would.

    Sometimes a DSP solution can be harder to crack than an ASIC. Especially
    if it contains nifty algorithms that run internally and where the code
    can't be read back out.

    Regards, Joerg
     
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