V
VSP
- Jan 1, 1970
- 0
Hello,
I am designing a SoC based system where I need to interface an 8255 PPI
with an ARM based CPU.
I am using memory mapped I/O for the interface. The problem is the data
bus pads of the SoC chip is not 5V tolerant. It can tolerate a 3.6V max
logic level swing on its data bus pads.
I dont want to use a level shifter circuitry because of cost issues.
Has anyone used an 8255 which can operate at 3.3V ? Is such a device
even available? Or could some one suggest some other chips which can
provide the functionality similar to 8255 but can work at 3.3V?
Thanks in advance!!!
Rgds,
VSP
I am designing a SoC based system where I need to interface an 8255 PPI
with an ARM based CPU.
I am using memory mapped I/O for the interface. The problem is the data
bus pads of the SoC chip is not 5V tolerant. It can tolerate a 3.6V max
logic level swing on its data bus pads.
I dont want to use a level shifter circuitry because of cost issues.
Has anyone used an 8255 which can operate at 3.3V ? Is such a device
even available? Or could some one suggest some other chips which can
provide the functionality similar to 8255 but can work at 3.3V?
Thanks in advance!!!
Rgds,
VSP