Anybody used the TC4432 (30v buffer)

[lerameur]

Hi,

I am trying to use the TC4432. I am doing the exact circuit of page 7
below. My Vdd is at 1v, and my input is coming from a pic chip running
at 10khz 60% duty cycle.

http://www.datasheetcatalog.com/datasheets_pdf/T/C/4/4/TC4432.shtml
page 7 of microchip

What I am getting at the output is oscillation between 10v low to 12v
high. The frequency is good, but it is not coming down to zero volt
like expected. Any body used this chip and can show me a working
circuit or have any ideas why that is?

thanks

K

 

[lerameur]

I am trying to use the TC4432. I am doing the exact circuit of page 7
below. My Vdd is at 1v, and my input is coming from a pic chip running
at 10khz 60% duty cycle.

TYPO
:I am trying to use the TC4432. I am doing the exact circuit of page 7
below. My Vdd is at -- 12v --- and my input is coming from a
pic chip running
at 10khz 60% duty cycle.

 

[Robert Monsen]

Hi,

I am trying to use the TC4432. I am doing the exact circuit of page 7
below. My Vdd is at 1v, and my input is coming from a pic chip running
at 10khz 60% duty cycle.

http://www.datasheetcatalog.com/datasheets_pdf/T/C/4/4/TC4432.shtml
page 7 of microchip

What I am getting at the output is oscillation between 10v low to 12v
high. The frequency is good, but it is not coming down to zero volt
like expected. Any body used this chip and can show me a working
circuit or have any ideas why that is?

thanks

K

Vdd is 1v? The minimum is 4.5V. I'm guessing you really meant
something else.

The Vdd must be between 4.5 and 30V, and the logic input switches at
0.8V and 2.4V. The output is 'open collector', meaning that you need
to pull it up to Vdd using a resistor in order to see any action.

Watch out for a floating UVLock pin.

3.3 Lockout Disable (LOCK DIS)
The lockout pin enables/disables the undervoltage
lock-out feature of the device. If undervoltage lockout is
desired (output is not enabled until the bias voltage
reaches 8.4V (typical) on the rising edge and is disabled
when the bias voltage reaches 7.7V (typical) on
the falling edge), the lockout pin should be left floating.
If operation below 7V is desired, the lockout pin should
be tied to ground.

Regards,
Bob Monsen

 

[Jamie]

Hi,

I am trying to use the TC4432. I am doing the exact circuit of page 7
below. My Vdd is at 1v, and my input is coming from a pic chip running
at 10khz 60% duty cycle.

http://www.datasheetcatalog.com/datasheets_pdf/T/C/4/4/TC4432.shtml
page 7 of microchip

What I am getting at the output is oscillation between 10v low to 12v
high. The frequency is good, but it is not coming down to zero volt
like expected. Any body used this chip and can show me a working
circuit or have any ideas why that is?

thanks

K

Maybe I've missed something here, the spec's state that Vdd starts at
4.5 V up to 30, You stated 1 volt? Maybe this is a clerical error and
should be like 10 volts ?

Also, the output Z is rated at 7 ohms, you must account for that as
it will influence the drive to the fet.

Have you placed a series R of around 10 or so ohms driving the
gate? If so, you could examine the signal via a scope and test for
a drop. It's very possible the driver isn't able to sink the output
enough.

You should try to test the output of the driver with no load or very
little load to determine the problem here.

It's possible the capacitance on the gate is excessive for the
driver to get the response you're looking for.



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