# Anti Aliasing Filter

Discussion in 'Electronic Design' started by [email protected], Jan 5, 2009.

1. ### Guest

It's the first time that i use anti aliasing filter, so i have some
doubts:
1)My signal has infinite frequencies, but greater frequencies have
lower harmonics.Is it correct to put fs/2 (fs=sampling frequency of
ADC) at frequencies where dynamic range of fitered signal is equal or
greater than dr of adc? In this way, i can use frequencies lower than
frequencies where filter attenuation is equal or greater than dr of
2)About noise,what should i consider?I want that noise, at frequencies
greater than fs/2, has Vpp lower than lsb. But (if noise has gaussian
distribution) Vpp=6.6Vrms: in what frequency range i should calculate
Vrms?
http://www.edn.com/article/CA6339244.html?industryid=2281
but i don't understand how slew rate is calculated....how can i obtain
SR from SR=dV/dt|max?
Thanks for the help and for any suggestion

2. ### MooseFETGuest

Usually the speed of the ADC is set by considerations other than the
filter's parameters and then the filter is designed to do what is
required. The "what is required" part of that depends a lot on the
application.
This part gets very tricky. If you imagine the desired signal not
being there then the RMS is the standard deviation of the signal.
This doesn't really tell you much about individual samples. When the
RMS goes below 1/sqrt(12) of the LSB, it starts to disappear into the
quantization noise.

You need to consider what exactly you require of the digitized
signal. The aliasing folds the spectrum over so that the frequencies
in the result are falling as the frequencies of the input are rising.
This means that the fall off of the filter appears as a bias towards
more noise at high frequencies.

You usually don't calculate the slew rate. It is usually a
consideration of the op-amps in the filter. You need to select op-
amps that won't distort the signal and noise that they are processing.

3. ### Guest

Thanks for the infos, i have another question...i have some problems
to calculate the right opamp's slew rate to obtain right adc accuracy.
i don't understand very well its datasheet
1)acquisition time: is it equal to sampling capacitor charge time plus
settling time?Is it fixed to 100ns?
2)In the settling time associated to sampling circuit, which effect
are considered?
slew rate?
In datasheet, Tcharge became significant with R2 (input impedance)
equal to 2K: in this case Tcharge shoud be equal to 56ns. So, if input
is equal to Vref, opamp should have Vref/56ns as slew rate....is this
right?
4)last question: at the beginning of sampling process, sampling
capacitor voltage is equal to Vdd/3?If so, why equivalent sampling
circuit (datasheet, figure 6) has C1 connected to ground?
Thanks for the help

4. ### MooseFETGuest

It depends a lot on how the sample and hold circuit is done. As the
internal switch turns off, there is a span of time over which changes
in the input voltage will effect the held voltage.
The simplest answer here is "all of them". Many years back, I worked
on a design where the power supply current changed when the sample and
hold was tripped. This caused a change in the supply voltage. The
change in power supply voltage effected things via the power supply
rejection ratio of an op-amp. We had to consider how much to lower
the supply impedance to bring this under one LSB of the converter.

The ADC is likely to contain its own internal buffer. If it does, the
slew rate is the slower of the two. If not, the op-amps slew rate
when working in to that much load should dominate.
No, the slew rate of an op-amp is only the case for the output moving
due to the inputs changing. It doesn't consider the effects of the