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AND logic gate woes

Discussion in 'Electronic Design' started by Elorg, Aug 29, 2004.

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  1. Elorg

    Elorg Guest

    Hello,

    I have a rather newbie question to ask - a project I've been building
    contains a triple AND logic gate from discrete components (namely 2sc857
    silicon NPN transistors from 1969, don't ask.)

    General idea is to clock a 4th cmos 4017 chip when all outputs of the
    first three 4017s, connected to the AND gate - are high. Thus the triple
    AND gate.

    The layout can be seen here:
    http://www.geocities.com/kawazmar/pic.gif

    (Excuse the inept drawing).


    However, I've had trouble getting this arrangement to run properly.
    Gates either triggered when only two conditionals were met, or failed to
    trigger altogether. It took four hours of tinkering with resistor values
    to get it running more-or-less reliably. It kept working for several
    weeks before quitting on me again.

    Yesterday I replaced one of the transistors and fiddled around with the
    resistor values - now the assembly works again, well, sort of, since it
    triggers when two out of three required conditionals are met.

    Now, it can't possibly be that difficult to build a working and reliable
    triple AND gate from discrete components; I'm probably doing something
    wrong. Any ideas?
     
  2. John Larkin

    John Larkin Guest


    Given the basic mystery here ("don't ask") try adding a 2K pulldown
    resistor from the bottom emitter to ground. This will

    a) give a logic 0 when you want it, and

    b) keep the diode action of the transistor b-e junctions from shooting
    through.

    You might also delete the 39K output resistor; it just slows down the
    clock.

    But, as others will confirm, this is not the best way to do this.


    John
     
  3. James Meyer

    James Meyer Guest

    You aren't the only one to have problems with AND gates. Even the
    professional logic manufacturers had problems. That's why most of their
    offerings are based on NAND gates or combinations of them. With a simple NAND
    gate you can synthesize any, and I do mean ANY, other logic function.

    For your application, obtaining an output when three inputs are "ones",
    you could use a simple three input NAND gate preceeded by three single input
    NAND gates. The single input NAND gate is just an inverter. A three input NAND
    gate will have a "zero" output when any of its inputs is a "one" and it's output
    will be a "one" when all of its inputs are "zero"s. Use the three inverting
    NAND gates to change the counter's outputs from "one"s to "zero"s. Then feed
    these "zero"s into your three input NAND gate.

    You will only have to add three more transistors and three more
    resistors to your original parts.

    Jim "Karnaugh" Meyer
     
  4. John Fields

    John Fields Guest

    ---
    Vcc
    |
    [10K]
    |
    4017OUT A>----|<-----+-----> ABC
    |
    4017OUT B>----|<-----+
    |
    4017OUT C>----|<-----+
     
  5. legg

    legg Guest

    Minimum pull-down has to sink two base currents with a voltage of less
    than VCC/3 , so less than 4K3 would be needed, with 33K base
    resistors.

    The same logic could be done with a simple diode (n)orring circuit,
    pulling down on an input with a single pull-up resistor. This reduces
    parts count by a factor of two, and the pull-up resistor could be ~any
    size, depending on speed requirements, reducing power loss.

    RL
     
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