John said:
That's an interesting all-discrete design.
A homebrew sampling oscilloscope would be an interesting project.
Equivalent bandwidths in the low GHz would be feasible. HP and Tek
were doing 4 GHz sampling scopes in the mid 1960's, with all
discretes, tubes actually.
John
I have been thinking that the ADCMP582 (fast latched comparator) would be an
interesting device for this kind of thing. It will tell you whether the
input waveform was above or below a specific value at a specific point in
time, and if you connect a DAC to the other input of the comparator, and if
the waveform is repetitive, then sooner or later you can figure out exactly
what was the voltage at a certain time point on the waveform.
To generate the sampling pulses simply, I was thinking of adding the
restriction that the waveform under test must be derived from stimulus
genetrated by a crystal oscillator inside the sampling scope. This would
be fine for doing TDR on cables and connectors, and evaluating the rise
time of logic gates etc.
If two voltage controlled crystal oscillators (VCXOs) were locked to
frequencies very close together (see * for how), then the edge from one
oscillator would "walk through" the waveform from the other oscillator very
slowly. This would eliminate the need for delay lines programmable with
picosecond resolution. One VCXO would be squared up (maybe by an ADCMP582)
and put out as the stimulus signal. The other VCXO would be squared up and
used as the clock pulse for another ADCMP582 used to digitise the input
waveform. The output of this comparator could control the Up/Down input of
a binary counter (also clocked by the comparator sampling clock VCXO) and
the counter binary output would in turn drive the DAC that provides the
reference for the digitising comparator, to form a tracking ADC. If the
input signal at the sampling point were to increase, the comparator would
cause the counter and DAC values to increase until the DAC output voltage
matches the input voltage to be sampled, at the sampling instant.
Provided the sampling VCXO walks through the stimulus VCXO waveform slowly
enough (the frequencies are similar enough), the up/down counter would be
able to make the DAC track the input waveform, and so the DAC output
voltage would be a greatly-slowed-down replica of the waveform to be
sampled, (but slew rate limited to 1 DAC LSB per VCXO cycle at the DAC
output).
* To lock the two VCXOs to very nearly the same frequency, but whilst using
wide bandwidth PLLs so that the close-in phase noise is good, the following
circuit is suggested, using two fractional-N synth chips like the ADF4156.
As an example, two 26MHz VCXOs out of old GSM mobile phones could be used,
as these are generally pretty high performance oscillators. The first VCXO
is set to mid-range and is allowed to free-run. This is the VCXO used to
produce the stimulus to the DUT. It goes to the reference input of the
first ADF4156. The feedback input of the first ADF4156 gets its signal
from the output of a microwave VCO, anywhere from 1.2 to 6GHz would do,
e.g. 2.7GHz, out of an old GSM phone would do. The charge pump of this
first ADF4156 would drive a loop filter which would drive the tuning input
of the microwave VCO. So far, this is a conventional microwave
synthesiser, and if the parameters of this first ADF4156 are set to
int=K(e.g. 104), frac=K (e.g. 104), mod=1999, then it will produce
26000000*(104+104/1999)Hz (roughly 2.705GHz) at the output of the VCO.
The output of the microwave VCO is also connected to the feedback input of a
second ADF4156, and the second VCXO (used as the sampling clock) is
connected to the ref input of this second ADF4156. The charge pump of the
second ADF4156 is connected to a loop filter which drives the tuning input
of the second VCXO, with the charge pump set with appropriate polarity so
that the second VCXO is locked to the microwave VCO. The parameters of the
second ADF4156 would be set to int=K, frac=K, mod=2000, so that the second
(sampling) VCXO would be equal to
= fVCO / (104+104/2000) Hz
= 26000000*(104+104/1999) / (104+104/2000) Hz
= 26000000*208000/1999 / (208104/2000) Hz
= 26000000*416000000 / 415999896 Hz
= 26000006.5 Hz
So using two wide-bandwidth PLLs, the oscillators can be locked 6.5Hz apart.
This means that the sampling waveform will sweep through the stimulus
waveform 6.5 times per second, with very low jitter. If the device being
tested would work better with a stimulus lower than 26MHz, then the
stimulus and sampling waveforms could be divided down.
If anyone has the time to build the above, I think it would be very
interesting. A proper microwave PCB would be very helpful to get the best
rise time perfomance. It might be feasible to see edges under 100ps, I
think.
Failing that, I have an old HP8411A that has two nice "Grove samplers" in
it, nominally 12.5GHz bandwidth. That cost only £40.
Chris