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analog ic layout

Discussion in 'Electronic Basics' started by fredo, Feb 7, 2006.

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  1. fredo

    fredo Guest

    i want to do an analog ic layout.
    where can i learn the technique?
    or will there be any internet resources for reference?
    or where would you recommend me to start.
    thank you.
     
  2. Chris

    Chris Guest

    Hi, Fredo. Start with these Analog Devices appnotes of general
    interest:

    AN-202: An IC Amplifier User's Guide to Decoupling, Grounding, and
    Making Things Go Right for a Change

    AN-345: Grounding for Low-and-High-Frequency Circuits

    AN-214: Ground Rules for High Speed Circuits

    http://www.analog.com/en/dcIndex.html

    By the way, "analog ic layout" isn't very specific. You might get more
    specific help if you could describe what you're doing.

    Good luck
    Chris
     
  3. fredo

    fredo Guest

    Chris 寫�:

    First of all, thanks Chris.

    Just one further question. If you are doing analog layout, how do you
    minimize the so-called parasitics to make it as ideal as in the
    schematic design? And how do you know if your layout has reached best
    optimization.

    I am working on a 0.35um technology with a rectifier design at UHF.

    Thank you in advance again.
     
  4. Chris

    Chris Guest

    Hi, Fredo. Try sci.electronics.design for advice on this one.

    Good luck
    Chris
     
  5. notme

    notme Guest

    You should get a book on analog layout such as "The Art of Analog Layout"
    by Hastings. The short answer to your question is, its something you get
    an intuitive feel for after you do a lot of times. You need to consider
    what nets are particularly sensitive to loading and then keep them away
    from other nets. Nets which are sensitive to Miller capacitance for
    instance you probably want to be most careful of.

    There are plenty of other issues besides parasitics. You also must worry
    about matching considerations. When laying out MOS transistors you want
    to be wary of the following:

    1) Matched transistors should be placed as close together as possible
    2) Matched transistors should be exact copies of each other.
    3) Matched transistors should have source-drain current flowing in the
    same direction
    4) Matched transistors should have dummy transistors placed on each end
    to ensure equal etch rates.
    5) Matched transistors should not have any metal run over them, or if
    its unavoidable the metal should run over both.
    6) The well or substrate tap spacing should be identical for both.
    7) Both Vt and Beta mismatch is inversely proportional to the square root
    of the gate area, so gate area should be large.
    8) If possible use a common centroid configuration (for instance breaking
    a pair of matched transistors into 2 pairs of matched transistors)
    where one pair is the outer two, and the other pair is in the inner
    two. 2-dimensional arrays are fine, but make it symmetric about the
    origin and make sure to have dummy transistors above and below.
    9) If you are matching a pair of transistors (such as a current mirror)
    over a long distance, the net should carry current into the drain of
    the mirroring transistor, not voltage to the gate.

    You should route signals differentially or shielded by a (CLEAN) ground
    if you are taking analog signals near digital ones. Analog and Digital
    power supplies should be seperated, and if possible ground as well (this
    is more important, but there is less you can do about it if you have a
    common substrate and can't put down P-wells). You also should consider
    using guard rings or other similar techniques.

    In general to improve routability, you should try to route all odd layer
    Metals in one direction, and all even layer Metals in the other. Avoid
    long runs of two nets above/below or to the side to decrease coupling
    (unless of course its differential). Also, try to use multiple vias when
    changing layers.

    Another consideration is the pads and ground/power bounce. The bondwires
    (unless you are using a flip-chip) are often quite inductive, there can be
    significant coupling between bondwires and significant LdI/dt power/ground
    movement especially if you have digital circuits on your chip. You need
    to make sure you have adequate bypass capacitance on the die.

    To answer your question regarding optimal. There's no such thing as
    optimal, and its a wildly underconstrained problem so even if there was an
    "optimal" solution the likelyhood that you'd find it is virtually nill.
    You are constantly faced with choices when floorplanning it, and as stuff
    is placed down the choices do become easier, but clearly the way to do a
    good job is experience. All you can do is extract it, and run a
    simulation with the parasitics in it and see how it does compared to the
    schematic. If its failing your design criteria then you may need to go
    back and tweak things.
     
  6. Get:

    "The Art Of Analog Layout" - Prentice Hall ISBN 0-13-087061-7 by Alan
    (Roy) Hastings

    http://www.amazon.com/gp/product/0131464108/ref=sr_11_1/104-6485116-0422310?_encoding=UTF8

    Kevin Aylward

    http://www.anasoft.co.uk
    SuperSpice, a very affordable Mixed-Mode
    Windows Simulator with Schematic Capture,
    Waveform Display, FFT's and Filter Design.
     
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