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An alternative to 74ls173's design ?

Discussion in 'General Electronics Discussion' started by asadmasad, Jun 19, 2018.

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  1. asadmasad


    Jun 19, 2018
    hi there,
    so i was watching a video about building a 1 bit register(made by Ben eater i guess). he explains that we have a SR flip-flop as the storing unit and we need to add a "load" to it so we have a register.
    then he starts adding some gates and he comes up with a design like the picture bellow.
    and then, i came up with an alternative design like this:
    and it worked. but when i continued watching the video, he introduced the 74LS174 which has the same design as he made :
    and now i keep thinking why is that ? i am sure that the engineers who designed this chip (and Ben) are experts and gave it a lot of thoughts. so what's the reason they made it this complicated ? is there a problem with my design ? or what ?

    thank you in advance and sorry if i was not clear enough,
    with regards,
  2. AnalogKid


    Jun 10, 2015
    The first circuit and your version work the same only for certain combinations of input signals. In your circuit, if the load input changes while the clock input is high, the ff is clocked immediately. In the original circuit, the ff is not clocked immediately, it is clocked on the next positive edge of the clock signal. In your circuit, there is a path from the load input to the ff clock pin. In the first circuit there is not; the load signal affects the data input, not the clock input.

    The inverter, OR gate, and 2 AND gates form a 2:1 multiplexer. Without that function, the circuits are very different.

    asadmasad likes this.
  3. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    Jan 21, 2010
    In addition to that, the internal circuit you see in the datasheet is normally labelled an "equivalent circuit" because the actual circuit may be quite different.

    As a very simple example, an xor gate may be shown as having an equivalent circuit consisting of a number of gated which implement the function "either input but not both" which will have a propagation delay being the sum of three gates through which the logic passes, however the implementation on silicon can take some shortcuts to achieve the result much faster. Similarly, there may be additional gates which appear to do nothing, but serve to ensure the propagation delay is correctly managed through multiple pathways.
    asadmasad likes this.
  4. asadmasad


    Jun 19, 2018
    I see. thank you.

    thanks a lot.
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