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Amplify 1.5v DC to 5v DC?

Discussion in 'Electronic Basics' started by [email protected], Oct 18, 2004.

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  1. Guest

    Hi

    I studied A-Level electronics about 15 years ago, and I've just got
    interested in electronics again. I'm very rusty, and the truth is
    that my analogue electronics was never very good anyway..

    I need to amplify a signal (actually, 4 of them, one being a clock
    pulse) from a digital line from an IC - it's either off - 0v or on at
    1.5v, nothing complicated. I need to feed this in to a PIC
    microcontroller, so it needs to be at 5v when high.

    I assume I'd want to use a transistor, feeding the 1.5v signal in to
    the base.

    Can I take the amplified 5v signal from a resistor connecting the
    emitter to gnd?

    I've had a bit of a google, and I never see this - only a resistor from
    +v to collector, but this will invert my signal - something I don't
    want to do.

    I have had a line-level converter chip recommended to me - MAX3001E,
    but this is only comes in very, very tiny TSSOP format, which would be
    difficult to solder up, but I'm interested in the transistor solution
    as this will help me to 'swat up' a bit on my A-level electronics.
    Regards,
    Mark
     
  2. No, you will only attenuate the signal to 0-0.8V.
    This circuit is known an "emitter follower" and does not amplify voltage.
    That's the common way to amplify voltages. You can use a two stage
    amplifier. That inverts two times so you get the right signal.
    Best thing I can advise is a LM393 or similar quad comparator. That contains
    four comparators so you need only one chip. Connect the inverting inputs to
    a voltage divider set to - let's say - 0.8V. A non inverting input for
    each of your input signals. As the outputs are open collector you may need a
    collector resistor. Depends on your PIC inputs (and their configuration.)

    petrus bitbyter
     
  3. Guest

    Hi

    I'll check out the quad comparators, thanks for the idea. Never used
    them before.

    Back to transistors though, because I really should get to understand
    these things. I obviously need to understand the first principals. So
    if you can't amplify voltage at the emitter, that infers that the
    current also isn't amplified at that point?

    Current is a flow rate, so where's the current going? I'd expect the
    current Ic to flow through the transistor, through the emitter and on
    to gnd (conventional current flow)? I thought that Ic = Ib*Hfe
    (roughly)? Shouldn't Ie then = Ib+Ic? Therefore if I put a resistor
    between emitter and gnd, I should get varying (& amplified) voltage
    across it because of ohms law?
    What am I failing to understand?

    Cheers,
    Mark
     
  4. No it doesn't the emitter voltage swing must be less than he base
    voltage swing, but the emitter current can be quite a bit larger than
    the base current (by the ratio of beta).
    And through whatever is between the emitter and ground.
    Well, Hfe varies as the collector to base voltage varies, but as long
    as the this voltage is above a few volts and the current is not too
    large, you can think of Hfe as something like a constant.
    The effect on the base current of that new voltage drop (the one
    across the emitter resistor). If the base current comes from a
    current source (a current that is independent of the voltage it passes
    in to), then this voltage drop does not change the base current. But
    if the base current comes from a voltage source through some
    impedance, then this resistor changes the voltage across that source
    impedance, and thus, the base current.
     
  5. Brian

    Brian Guest

    In the emitter-follower configuration, you get current gain but not
    voltage gain. In this configuration, the emitter must be about 0.7 volts
    less than the base voltage (otherwise the transistor will not conduct at
    all). With an emitter resistor in the circuit, the emitter voltage will
    follow the base voltage (minus the approx. 0.7 volts).
    Brian
     
  6. CFoley1064

    CFoley1064 Guest

    Subject: Amplify 1.5v DC to 5v DC?
    Hi, Mark. The "classic" way to do this would be with a quad comparator like
    the LM339. You would set a reference level at about half of your 1.5V, and
    then use the comparator to give you the logic level outputs, like this (view in
    fixed font or M$ Notepad):

    ___
    .---|___|- VCC
    ___ V |\ | 10K
    VCC -|___|-o----|-\ |
    10K | | >-o-------------o
    o-------|----|+/
    | |/
    |
    | ___
    | |\ .---|___|- VCC
    o----|-\ | 10K
    | | >-o-------------o
    o-------|----|+/
    | |/
    |
    | ___
    | |\ .---|___|- VCC
    o----|-\ | 10K
    | | >-o-------------o
    o-------|----|+/
    | |/
    | VCC
    | + ___
    | |\| .---|___|- VCC
    o----|-\ | 10K
    | | >-o-------------o
    o-------|----|+/
    | |/|
    | ===
    V GND
    1N4001-
    |
    ===
    GND
    created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de

    The 10K resistor in series with the diode establishes an 0.7V reference V at
    the four inverting terminals. Your four 0V/1.5V input signals are applied at
    the non-inverting terminals, and the outputs (with 10K pullup resistors) go to
    your PIC.

    Good luck
    Chris
     
  7. I don't think so, as the NPN emitter will have a voltage that is lower than the
    base, if it's operating normally. It doesn't invert, but the lower voltage will
    be the problem.
    Ah. Okay. Then you probably need a second transistor, perhaps a PNP, to
    reinvert it, again. A little more complexity.
    Understood. It's about how I'd feel, too, I think. (TI and others do make ICs
    for level shifting, which include two power pins for the purpose, in fact. But
    doing it with BJTs means you can understand the basic ideas.)

    As you already know, the inverter is:

    5V
    |
    |
    \
    / R2
    \
    |
    +-----> out
    |
    R1 |/c
    in >--/\/\----| Q1
    |>e
    |
    |
    gnd

    The above circuit assumes that 'in' is an active, low impedance drive for both
    0V and 1.5V and just uses Q1 as a saturated switch, more or less, allowing the
    collector to get very close to the base voltage of 0V, or probably about .2V or
    so. But that only happens when 'in' is at 1.5V and turns on Q1's switching
    function. And when that happens, as you already know, 'out' gets very close to
    0V, which is the opposite of what you want happening.

    To invert the inverter:

    5V
    |
    |
    \ 5V
    / R2 |
    \ |
    | |<e
    +----| Q2
    | |\c
    |/c |
    in >----| Q1 +-----> out
    |>e |
    | \
    \ / R3
    / R1 \
    \ |
    | |
    gnd gnd

    There are actually several different arrangements. One would look more like the
    first case, with a base resistor like before for Q1. But this works, too, and
    it does things a little differently. In this case, Q1's base is "tacked" hard
    to the low-impedance drive and thus the emitter is forced to follow closely.
    This impresses a voltage on R1 which allows you to calculate a fairly precise
    current that you want to flow -- roughly a 'programmable constant current' that
    is presented via the collector of Q1 and is driven through R2 and Q2's base.
    Now, you could add another resistor to Q2's base, too, to allow the base to
    'find it's place'. But if you are careful in designing R2 and R3, it's not
    really necessary -- you just make sure that there is slightly more than enough
    current to force Q2's base down adequately, when calculated through R2, and
    allow enough margin to operate Q2's collector current via some modestly
    predicted beta.

    For example,

    Q1 = 2N3904
    Q2 = 2N3906
    R3 = 47k (perhaps stiff enough for PIC inputs)

    Now, you might decide to lower R3 to make it somewhat stiffer or raise it. What
    you choose here will depend some on the loading that needs to be driven. But
    PIC inputs (like most micro inputs) don't require more than 10uA and 5V across a
    47k yields about 100uA from which 10uA won't hurt much. But read the data sheet
    and make sure about this and set the expected current through R3 to be some 10X
    over the worst case you have to deal with.

    Okay, so to continue. When Q2 is 'on', we'll project that the beta will be
    about 50 (normally, when V(CE) is a few volts the 2N3906 is often showing a beta
    4-6 times this much beta, so we can expect a V(CE) of say 0.3V at a beta of 50,
    I think -- but I'm guessing here.) This suggests that the voltage across the
    47k is 4.7V for a collector current of 100uA.

    With a collector current of 100uA and a guessed beta of about 50, the base
    current needed will be 100uA/50 or about 2uA. So, let's plan to use 4uA drive
    from Q1, doubling this estimate. We know that when Q1 is 'on', the emitter
    voltage will be something circa 0.7V. But with such low currents (4uA) it will
    probably be closer to more like 0.5V. So, let's guess at that number for now.
    The emitter of Q1 will then be 0.5V less than the base, which we know to be
    1.5V, so the emitter voltage will be 1.5V - 0.5V or 1.0V. We know that we want
    about 4uA emitter current (this transistor's beta will be pretty high, so the
    base current will be negligible) and thus, R1 = 1.0V/4uA or 250k.

    Now, R2 will need to provide about 0.6V (another guess, I'm making) at 2uA (it's
    'half' of the allotted 4uA.) So, this implies R2 = 0.6V / 2uA or 300k.

    So, let's try:

    R1 = 220k (a little more drive current, just in case)
    R2 = 270k (to suck up just a little more of that drive current)

    We have a design?!

    5V
    |
    |
    R2 \ 5V
    270k / |
    \ |
    | |<e
    +----| Q2
    2N3904 | |\c 2N3906
    |/c |
    in >----| Q1 +-----> out
    |>e |
    | \
    \ / R3
    R1 / \ 47k
    220k \ |
    | |
    gnd gnd

    How does this simulate? Well, I get about 0V to 4.9V swings on the output,
    given 0V to 1.5V swings on the input. And it looks pretty clean. Simulated
    estimates are:

    Q1 base current average of some 20pA with spikes on the transitions reaching as
    much as 1.5uA (chances are, your drive to this circuit can handle that.) I(R1)
    is more like 4.5uA instead of the 4uA we planned. But R1 is 220k instead of
    250k, too. So we expected something extra here. I(R2) is about 2.2uA, instead
    of the planned 2uA, but again we had adjusted it down a bit to suck up some
    extra -- and it does. Base current on Q2 is about the same, 2.2uA (the
    unaccounted for 0.1uA is actually just rounding errors I'm making.) Collector
    current on Q2 is very close, too, at a bit less than 105uA.

    In other words, it's seems to hold up.

    But none of this takes care of speed issues. You didn't mention how fast your
    logic and clock pulses may be.

    If you want something with active drive HI and LO and that is faster, try
    something along these lines:

    R3 || 2200pF
    ,------------/\/\----||--------------,
    | 470 || C2 |
    | |
    | 5V 5V |
    | | | |
    | | | |
    | | 1N4148 | |
    | \ D1 --- |
    | / R1 / \ | 5V
    | \ 22k --- | |
    | / | | |
    | | | | |
    | | | | |<e Q2
    | +-------------+------+-----| 2N3906
    | | |\c
    | 1.5V | |
    | | |/c Q3 |
    | '------| 2N3904 |
    | |>e |
    | | |
    | | |
    | ,-----+ +---> OUT
    | | | |
    | | \ |
    | | / R2 |
    | C1 --- \ 22k |
    | 470pF --- / |
    | | | |
    | | | |
    | | | R4 |/c Q1
    IN >---++--------+-----+----------/\/\------+-----| 2N3904
    | 10k | |>e
    | | |
    | C3 | |
    | R5 || 1000pF | |
    '-----------/\/\----||--------------' gnd
    750 ||

    In this case, R3+C2 as well as R5+C3 are "speed up" sections to help propagate
    an edge forward. The rest is interesting to read through and get an eye to how
    it works.

    I haven't been careful about the designing the values here, because I've no idea
    if you really care about something like this. Also, it again is an inverter and
    you'd need to take some care about making this into a non-inverting circuit.
    The point is mainly that for fast circuits you may need to do a little more than
    something dead simple.

    Jon
     
  8. The absolute voltage on the base, relative to some random ground
    somewhere, is not relevant. What really matters, and what determines
    the collector current is the _relative_ voltage between base and
    emitter.
     
  9. joji john

    joji john Guest

    Current is a flow rate, so where's the current going? I'd expect the
    To explain this you will have to dig deep into the construction of the
    semiconductor transistor. Lets refer to the npn transistor.
    You have connected something like this:
    Vcc (+5V) to collector; input to base; and emitter
    to a resistor and you are tapping the voltage across the resistor wrt
    ground? Correct me if I'm wrong.
    The transistor may be simplified and thought of as 2 junctions on n-p
    junction (Collector-Emitter) and another p-n junction (Base-Collector).
    Junctions here may be akin to diodes for sake oof simplicity without loss of
    detail.

    Now when the base is at 0 V and the collector tied to 5V whic makes
    p-side=0V and n=5V which reverse biases the collector base junction(diode)
    which results in just minimal (reverse) current injected into the emitter
    side from collector. The base -collector has no potential dufference.

    Now when the voltage at the base is pumped up to 1.5 V, still the CB
    junction is reverse biased but the threshold voltage for the base-emmiter
    voltage is exceeded (roughly 0.7-1V) and the considerable forward current
    flows to the collector from the base. Remember CB junction is still reverse
    biased and minimal (microamps) of current os sourced from collector side.
    Now after the 0.7-1V drop across the BE junction the volatage at the
    resistor is hardly a fraction of the input (no amplification) and shape of
    the output is smilar t input ; thus "follwing the input".

    THink of the transistor as two switches if you still find it difficult to
    follow.
    I hope you can follow .
    Joji
     
  10. Guess you fail to know some facts about transistors. That Ic=Ib*Hfe is a
    good one to remember but it is only valid under some conditions. One is that
    the base-emitter diode should be forward biased. A forward biased silicium
    diode requires some 0.6V across it. Another is that the transistor should
    not be saturated. Even within this conditions Hfe is not contstant over the
    whole Ic range.

    If you build an emitterfollower, with Vcc =5V and an input voltage of 0V the
    base-emitter diode is not forward biased. There will be neither Ib nor Ic
    except from some leakage.

    If you raise Vin to 1.5V some Ib will flow generating an Ic and both will
    flow to the emitter. Out of the emitter it mets the resistor and will build
    some voltage across it. This voltage can be calculated easily. A 1.5V input
    minus a 0.6V forward biased diode gives 0.9V left over for the resistor.
    This voltage is - within reasonable limits of course - independent of the
    resistor. If you lower the resistor, Ib will increase and Ic will raise
    accordingly until the forward biased base-emitter diode is about 0.6V and
    again there is 0.9V left for the resistor.

    You can also raise Vin to let's say 2.5V. Again. the currents increase,
    keeping Vbe at about 0.6V and left 1.9 for the resistor. So the voltage on
    the emitter follows the voltage on the base minus that 0.6V. Which explains
    the name emitterfollower.

    If you really want to do more with electronics I advise to get some book.
    Horowitz for example wrote a good and wellknown one.

    petrus bitbyter
     
  11. I thought I'd expand by adding some of those possibilities and then asking the
    experts for their analysis. I prefer the above arrangement because it appears
    to do better on power and on speed. But here are some other arrangements (and
    why not add more if you want to...):

    One interesting one is something like this:

    5V
    |
    |
    \
    / R2
    \
    |
    1.5V +----> out
    | |
    | |/c
    '----| Q1
    |>e
    |
    |
    \
    / R1
    \
    |
    in >------'

    In this case, the signal remains non-inverted and it uses a single transistor.
    However, the output doesn't quite make it to ground. More like about 1.1V or
    so. I kind of look at this as 'yanking the chain' on Q1, as Q1 is nailed down
    to the 1.5V and the input "pulls" a current, when low.

    It's fairly fast. But what makes it faster than other choices below?

    In any case, this was the basis for the faster circuit I'd mentioned on the
    previous post -- with the right values, the circuit can produce just the right
    range of pulses for driving a 'high-side' transistor. And if you look, you'll
    see this little piece in the three transistor circuit in the previous post.

    Two other circuits, poorer I think than the two transistor one I offered up
    earlier, follow. This next one is the worse of the two:

    5V
    |
    |
    \ 5V
    / R2 |
    \ |
    | R4 |<e
    +--/\/\--| Q2
    | |\c
    R1 |/c |
    in >--/\/\--| Q1 +-----> out
    |>e |
    | \
    | / R3
    gnd \
    |
    |
    gnd

    Very slow.

    Here's a faster one, almost as fast as the early one I mentioned:

    5V
    |
    |
    \ 5V
    / R2 |
    \ |
    | |<e
    +--------| Q2
    | |\c
    \ |
    / R4 +-----> out
    \ |
    | \
    R1 |/c / R3
    in >--/\/\--| Q1 \
    |>e |
    | |
    | gnd
    gnd

    Would any of the resident experts care to discuss these variations on a theme
    (or the ones in my previous post) and offer others, perhaps? I think it could
    be useful to see how one approaches thinking about these.

    Jon
     
  12. KM

    KM Guest

    HI,
    I am not sure if it works for you, you can try this

    When the digital line is logic low at 0 volt the transistor turn on
    and current flow via the resistor R2. (choose R1 & R2 to be loage
    value eg. 47k not to stress the IC sink cabability ) and when the the
    line turn to high the transistor turn off.

    Good luck!
    KM
     
  13. Thanks! After my first post on this (where I'd entirely forgotten to mention
    the method), I decided to dance around your posted circuit in my second post but
    to hold back from actually posting it until a third addition I wanted to make
    today, wondering if someone would mention this exact alternative! Now, no need.

    Some hobbyist thoughts:

    A fair design might use a 220k in the base, planning a current gain of only 25
    for reasonable saturation, ((5-.2)/47k)/((1.5-.6)/220k), and not much increase
    in drive current over what's already needed. However, it's speed tops out at
    about 50kHz or so, while still pulling 100uA drive current when low. My first
    posted example design (using 1/2 sized R1 and R2 of what I posted) is also good
    to about 50kHz, but by comparison pulls only tens of nanoamps of drive current.
    Also, my second post which includes the circuit quite similar to yours, but with
    the base resistor removed and an emitter resistor added, and designing it for
    about the same 100uA drive current and similar output impedance yields a top
    speed of about 500kHz -- 10 times better. The output swing is a little less, 4V
    instead of 5V, but that's not enough to account for the difference. Why then?

    Jon
     
  14. Guest

    Hi

    I downloaded PSPICE, and simulated a couple of your suggested circuits.
    Jon your first non-inverting circuit with the pair of transistors
    NPN&PNP - I get the same results as you, using a DC sweep on the input
    from 0v to 1.5v in 0.1v steps. Although, the IQ2 (IIRC) was negative -
    is that what you'd expect because of the PNP transistor?

    However, I can't get anything to happen with the later suggested
    single transistor cct with the input at the emitter, and base held
    permanently at 1.5v - I get the collector permanently sitting at 5v
    across the whole input sweep. With or without a resistor on the
    emitter and collector, both 47k as suggested.

    Your fast switching, but inverting with three transistors, feed back(?)
    and capacitors totally lost me I'm afraid. I'm interested to learn
    what's going on here if you have the time to explain.

    Speed wise, I don't think I need anything too fast - the clock pulse
    duration is 1.25ms, I make that 800Hz, is that right? So nothing too
    complicated/fast is required anyway.

    I did find a couple of IC's yesterday for level shifting, but they are
    14-pin and do additional stuff, which I don't really need. The IC's I
    found were Texas Instruments CD40109B - CMOS Quad Low-to-high voltage
    level shifter, and ON Semiconductor MC14504B Hex Level Shifter for TTL
    to CMOS or CMOS to CMOS. The TI chip has enable pins in addition -
    which I don't care about and can just fix enabled, but the ON looks
    somehow simpler, but has this TTL/CMOS level switch configuration - I
    think I need to configure it for TTL to CMOS for 1.5v to 5v level
    shifting? Which do you prefer? Or can you suggest something simpler?
    Cheers,
    Mark
     
  15. Spice uses an entirely consistent point of view for currents. But it isn't
    always obvious from looking at a schematic. In the case of one I occasionally
    use, flipping a resistor's orientation inverts the reading when I click it. Yet
    it looks the same on the schematic. I suspect this has nothing to do with the
    way spice analyzes it, but everything to do with the way the resistor's pin
    numbers are seen by the GUI interface and mapped back to the currents. I live
    with it. To be honest, I don't usually worry about the sign of the current
    because I usually know what it's supposed to be doing.
    This one?

    5V
    |
    |
    \
    / R2
    \
    |
    1.5V +----> out
    | |
    | |/c
    '----| Q1
    |>e
    |
    |
    \
    / R1
    \
    |
    in >------'

    If so, just plug in R2=10k and R1=2k, for one example. But I'm not sure what
    you are doing, so it's hard to say. If you set both R1 and R2 at 47k, I think
    the behavior should be that since you get only about 1V across R1 that you'd
    only get about 1V across R2, so I wouldn't expect the collector to go lower than
    4V. But I would expect something when the input is near 0V in your .dc
    analysis. I assume you are specifying the input source for your .dc analysis,
    right?
    It should wait until you understand the above circuit better, since that is one
    third of the transistor sections in it. And keep in mind I'm only a hobbyist
    and do not have all the better intuitions here. But I do think I can explain
    the basic aspects and let others correct me where they feel the need, when you
    feel you can follow the above circuit.
    That's VERY easy, then. In this case, KM's suggestion is excellent. Very few
    parts and it works well. I'd try a 10k in the collector and a 56k in the base,
    for example. I don't know if you have a scope, but if for some reason the low
    voltage on the collector isn't quite as low as you'd like, you can reduce the
    56k somewhat. But I think a beta of 30 should be fine for reducing the V(CE)
    near enough to zero. I don't think going much below 30 will buy you much in
    getting the lower voltage any closer to 0V.
    I've not used any of these (I'm a hobbyist, remember?), but I'm sure that folks
    like Spehro or others will be able to tell you some useful information.

    'simpler' to me would be using the BJT in KM's arrangement. Of course, with
    lots of LEDs, maybe one of the ICs would be 'simpler.' There are also some very
    fancy ones designed exactly for serial loading and driving up to some 36 LEDs
    independently in a single (big) package. But I also hate TQFPs and SC70s and
    their tiny little pins for surface mounting, when all I'm trying to do is just
    make something fun in a one-off. I'd much prefer to just wire-wrap or solder.
    So that would push me back to the BJT unless I could find a DIP IC that fits
    nicely into a wire-wrap socket or else buy a cheap pc board adapter for
    something I could solder well.

    I'm a TO-18 kind of person, I guess.

    Jon
     
  16. Rich Grise

    Rich Grise Guest

    I'd suggest putting the NPN on the PIC side even for the "simpler"
    circuit(s), since traditionally, TTL outputs have an NPN there, and the
    inputs source current. These days it's probably irrelevant, but you might
    be interested in the effects on rise/fall times with either the NPN or the
    PNP drive.

    Have Fun!
    Rich
     
  17. Guest

    Ok, I just simulated this R2=10k, R1=2k, flat line at collector ~5v.
    Using NPN transistor, correct?

    Can you explain your thinking for this idea? I assume that it's ok not
    to have a gnd in the cct(emitter), because the current flows from the
    lesser voltage to the greater voltage (in reality, opposite in
    conventional flow).

    Say for 0v input, ignoring base, I'd expect about 4.16v at the
    collector - potential divider R2/(R1+R2)*5v?
    for 1.5v input, R2/(R1+R2)*(5-1.5) = 2.91v????

    I'm struggling to understand this. And I'm not seeing it simulate
    either, which doesn't help! :)

    Cheers,
    Mark
     
  18. Yup, NPN. I'd say there is some problem in your schematic. The netlist should
    look like:

    Q1 3 1 2 2N3904
    R1 2 0 2k
    R2 4 3 10k
    V1 4 0 5
    V2 1 0 PULSE(0 1.5 0 0 0 20u 40u)

    If you use something like the above, then it's node 3 you should monitor as the
    output. Can you read 'netlists' and make a schematic on paper from them?
    The ground should be connected as shown in the above netlist, and not to the
    emitter. You can perform a .dc sweep on V2 above or else just do a .tran.
    For 0V at the base in the above circuit (netlist), the NPN will be off, so no
    current will be flowing through the 10k, at all. Since the voltage drop is
    10k*I and since I=0, there is no drop. So the output at node 3 (the NPN
    collector) would be 5V.
    Understood -- your logic above sure looks wrong to me. But maybe the first
    thing is to get it simulating right. Can always deal with the explanations,
    later.
    I think it's the schematic you are using. If I saw all the details, I think I
    could point out the problem.

    Jon
     
  19. Guest

    Hi Jon

    Is it possible in PSPICE to generate a schematic from the NETLIST?

    Anyway, I think I understand how they work - just the transistor
    numbering to understand. From my own schematic, I think the sequence
    is c-b-e. Working with that, I get input in to base of Q1, resistor R1
    at emitter, and R2 at collector. That's not what I was modelling. I
    thought we were discussing providing an input to the emitter? That's
    what I was attempting to model.

    I'm fine understanding a cct, which provides a signal in to the
    transistor base, but this will invert, won't it? I thought there was a
    proposal for a non-inverting, single transistor amplifier for my data
    lines, which took an input in to the emitter?

    What difference does it make, having R1 in the cct (in your netlist
    above) then?

    Also, why the preference for a NPN-PNP transistor pair for a
    non-inverting cct (in your previous posts), and not just a collector of
    one NPN feeding in to the base of another NPN?

    Cheers,
    Mark
     
  20. It *would* be easy for the software to just drop down the parts with the
    indicated connections, but I'm not sure how it would also decide what "looks
    good" to your eye. It might even just lay the parts on top of each other in a
    kind of "rat's nest" and you'd have to tease it apart, visually.
    Yes, Q1 is "node 3" as collector, "node 1" as base, and "node 2" as emitter,
    with the transistor being a 2N3904.
    Yes, from V2 as the pulse generator.
    Yes. Of course, you didn't mentioned where the other end of any of these went,
    but I can assume you can figure it out from what you've already said.

    Please note that node 0 is always "ground".
    Okay. I figured there was a disconnect between us going on.
    My mistake, then. With all the various options floating around, I guess I
    didn't know *what* you were simulating. Here is what I imagine, now:

    +5
    |
    / R1
    \ 47k
    /
    |
    +---Vout
    |
    R2 |/c Q1
    +1.5--/\/\--| 2N3904
    220k |>e
    |
    pulse
    input (1.5V pulses)
    |
    gnd

    or,

    Q1 Vout 2 IN 2N3904
    R1 V5 Vout 47k
    R2 2 V1.5 220k
    V1 V1.5 0 1.5
    V2 V5 0 5
    V3 IN 0 PULSE(0 1.5 0 1n 1n 625u 1.25m)

    That is from KM's post, with values I suggested.
    First off, I had thought you were curious about that circuit because it is used
    as one part of that more complex circuit you asked about. Not because I
    believed you'd actually use it, since it doesn't do what you want. It inverts
    the input, for one thing, and I already know you don't want that. Second, it
    doesn't provide anything like a 0V to 5V output span and I know you want that.

    That said, in that example the emitter resistor is required because the input
    pulsing is directly coupled to the base. You cannot reasonably expect to have
    1.5V across the base-emitter diode without absolutely HUGE base currents
    flowing. Placing a resistor on the emitter leg allows the emitter to "float"
    with the base. It would simply be "bad news" without it. Of course, you could
    use a base resistor but then that's a different topology.
    There were several examples provided, but all of them would just leave the
    signal inverted if the output transistor were replaced with an NPN. Plus, the
    output levels would be 'way off,' as well. Perhaps, if you were to expose your
    own thinking on this question, I (or someone) could help you see better why this
    is so. It's hard to guess what you are thinking, when all you do is suggest a
    part change. Try writing more about why you think it may work okay.

    Jon
     
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