algorithm for micro controller

[vead]

hello experts
I want to write verilog code for microcontroller (8051)

I have done little homework
designing controller is not easy so I have divided my homework
first I have developed algorithem

(algorithm )

Design for microcontroller

Verilog code

What is Input for microcontroller

What is Output for microcontroller

// I write module for microcontroller

//input deceleration

// output deceleration

// interconnect signal

// I make inner part (alu decoder pc timer….)

// I route all inner part

Endmodule

I have applied this algorithm And I made following handy code I know there are so many error

// module for microcontroller
module mcu_8051(clk,rst,p0_in,p1_in,p2_in,p3_in,p0_out,p1_out,p2_out,p3_out,rx_in  tx_out ,into,int1,to_in,t1_in,wr,wd , op_in, op_out, scr1,scr2,scr3

// input and output declaration

// port        
p0_in, p1_in, p2_in, p3_in;        // port input
p0_out,p1_out,p2_out,p3_out  // port output

// clock input
Clk;                         // clock input

//rest input
Rst                         // reset in input

//Uart
rx_in                         // receive
tx_out               // transmit

//timer
to_in,                                            //timer t0 input
t1_in                                             // timer t1 input

// interrupt
int0,                                             // interrupt 0 input      
int1                                             // interrupt 1 input        

//alu

src1,       // alu source 1
src2,       // alu sources 2
src3,       // alu sources 3

//decoder
Opcode_in    // operation code input
Opcode_output // operation code output

// program memory
Rd_in       //  read input
adr_o     // input
data_out   // data ouput

// data memory
Rd_in   //  read input
Wd_in     // write in
Adr_in     // address input
Data _in    // data input
Data_out    // data output

Interconnect signal
             input[ 7:0] p0_in
             inpu[7:0]p1_in
             input [7:0] p2_in

input [7:0]p3_in
output [7:0] p0_out,
output [7:0] p1_out,
output [7:0] p2_out,
output [7:0] p3_out,
wire [7:0]opcode_in
wire [7:0]opcode_out
wire [7:0] acc
wire [7:0] pc
wire [7:0] data_in
wire [7:0] data_out
wire [7:0] scr1
wire [7:0] scr2
wire [7:0] scr3
wire [7:0] opcode_in
wire [15:0]pc ;

// add port p0
Module mcu_port0(input, output)
Input ..;
Output…;
Endmodule

// add port p1
Module mcu_port1(input, output)
Input ..;
Output…;
Endmodule

// add port p2
Module mcu_port2(input, output)
Input ..;
Output…;
Endmodule

// add port p3
Module mcu_port3(input, output)
Input ..;
Output…;
Endmodule


// add alu
module mcu_ alu (a,b,s0,s1,s2 f);
Input a,b,s0,s1,s2;
Output f;
Reg [3:0];
Always @(s0,s1,s2);
Begian
Case (s0,s1,s2);
3b’000 :f=(a&b);
3b’001:f= (a|b);
3b’010 :f= ~(a&b);
3b’011 :f= ~ (a|b);
3b’100:f=(a^b);
3b’101: f=(a*b);
3b’110: f=(a+b);
3b’111:f=(a-b );
End case;
endmodule

//Add decoder
Module mcu_ decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
Input a2,a1,a0;
Output d7,d6,d5,d4,d3,d2,d1,d0;
Wire [7:0];
Always @(a2,a1,a0);
Begin
Case (a2,a1,a0);
4’b000: (d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
4’b100: (d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
4’b101: (d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
Endcase
endmodule

//add counter
module mcu _counter(current state, next state ,clk)
input current state ;
input clk;
output next state;
reg 3:0
always @ (posedge clk);
begin
next state <= current state +1 ;
end
endmodule

‘’’’’’’’
;;;;;;;;;;;;;
;;;;;;;;;;;;;;
End other component
endmodule

don't write all code for me I need guide to check my homework. I want guide that will give me task to do . I will do homework. how to improve code
I am reading tutorial , pdf files , I am searching this topics on internet
please help me

 

[Fish4Fun]

vead,

First Verilog//HDLs//FPGAs are NOT really in my wheelhouse....but, I assume you are attempting to synthesize an 8051 on some specific FPGA demo board/platform? I am certain you must be aware of public domain libraries like: http://www.cs.ucr.edu/~dalton/i8051/i8051syn/ ? The 8051 core is likely the most commonly synthesized core and as such every nuance is discussed somewhere...and many dev kits come with 8051 cores as "example code"....lots of EDU docs...etc...but knowing that the information exists is about as far as my knowledge goes...HDLs//FPGAs are fascinating and powerful tools...and one day I hope to find the time to learn a bit about them...but they are not exactly "mainstream consumer" devices. There are some very bright and electronics savvy members here, and I don't want to suggest there aren't members here who might be able to help, but if no one responds, finding "help" or a "guide" to help in any particular synthesis might require finding a forum more specifically dedicated to FPGAs/Verilog....and even then will likely require a very self-disciplined self-study approach.

Good Luck!

Fish