Agilent 62Ghz scope Demo and experiments

[amdx]

A few of you, very few, may want to drewl over this bleeding edge scope.
http://thesignalpath.com/blogs/2013...ilent-dsa-x-96204q-160gss-62ghz-oscilloscope/

Mikek

 

[Jamie M]

The million-dollar oscilloscope can't be far away.

And a $350 Rigol is a better scope than something that cost $10K not
too long ago.

Hi,

Wow thats a nice $500,000 scope.. It also looks like something that
could be homebuilt! Its a 4channel 80GSPS, looks like 8x
interleaving per channel, so that would be 8 10GSPS ADC's (8bits each)
per channel. The hard part might be getting the low jitter clock
running to feed the ADC's for interleaving them, but the phase delay
on the interleaving once set correctly via fine tuning of the trace
length or whatever should be doable I guess! Sounds like a fun weekend
project!

cheers,
Jamie

 

[Joerg]

Hi,

Wow thats a nice $500,000 scope.. It also looks like something that
could be homebuilt! Its a 4channel 80GSPS, looks like 8x
interleaving per channel, so that would be 8 10GSPS ADC's (8bits each)
per channel. The hard part might be getting the low jitter clock
running to feed the ADC's for interleaving them, but the phase delay
on the interleaving once set correctly via fine tuning of the trace
length or whatever should be doable I guess! Sounds like a fun weekend
project!

You usually need to electronically tune the aperture delay. BTDT. Not at
10GHz but "only" 100MHz or so and 12-bits. However, the client didn't
want to see any residual stuff down to -100dB which made this a nice
challenge.

 

[Mark]

A few of you, very few, may want to drewl over this bleeding edge scope.
http://thesignalpath.com/blogs/2013...ilent-dsa-x-96204q-160gss-62ghz-oscilloscope/

What about Lecroy's 100GHz scope?

 

[[email protected]]

A few of you, very few, may want to drewl over this bleeding edge scope.
http://thesignalpath.com/blogs/2013...ilent-dsa-x-96204q-160gss-62ghz-oscilloscope/

That is a bit slow

How do you troubleshoot 40 Gbit/s optical link systems ?

Apparently with repeated patterns and subsampling ?

 

[Jamie M]

You usually need to electronically tune the aperture delay. BTDT. Not at
10GHz but "only" 100MHz or so and 12-bits. However, the client didn't
want to see any residual stuff down to -100dB which made this a nice
challenge.

Hi,

Would it be possible to use something like a tank circuit as a jitter
reducer on a cheap clock? Like if the tank circuit operates at the
same average frequency as a clock, it can store energy for more than one
cycle and lock in the frequency perhaps so there is less jitter and the
cheap clock source could keep the tank circuit energized, this would be
a 1GHz to 10GHz tank.

cheers,
Jamie

 

[Phil Hobbs]

Hi,

Would it be possible to use something like a tank circuit as a jitter
reducer on a cheap clock? Like if the tank circuit operates at the
same average frequency as a clock, it can store energy for more than one
cycle and lock in the frequency perhaps so there is less jitter and the
cheap clock source could keep the tank circuit energized, this would be
a 1GHz to 10GHz tank.

Turd-polishing like that can help a bit in marginal situations, but it's
far from a complete solution.

Cheers

Phil Hobbs




--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058

hobbs at electrooptical dot net
http://electrooptical.net

 

[Joerg]

Hi,

Would it be possible to use something like a tank circuit as a jitter
reducer on a cheap clock? Like if the tank circuit operates at the
same average frequency as a clock, it can store energy for more than one
cycle and lock in the frequency perhaps so there is less jitter and the
cheap clock source could keep the tank circuit energized, this would be
a 1GHz to 10GHz tank.

It works differently. You take a super squeaky clean clock, goes into a
divider, send one of the divider outputs through a fixed delay network
and then on to the first ADC. The others get theirs via electronically
adjustable delays. Best to use a servo structure in there so the
processing math workload is low, resulting fast convergence. Then send a
test signal through there with an odd divide ratio and lowpass it a bit.
For example, a divide ratio of 9 if you have 8 ADCs. Now the 2nd ADC's
delay circuit is adjusted until the 9th conversion result is the same as
the 1st, the 3rd ADC's circuit until the 18th result is the same as the
1st, and so on.

 

[Jamie M]

It works differently. You take a super squeaky clean clock, goes into a
divider, send one of the divider outputs through a fixed delay network
and then on to the first ADC. The others get theirs via electronically
adjustable delays. Best to use a servo structure in there so the
processing math workload is low, resulting fast convergence. Then send a
test signal through there with an odd divide ratio and lowpass it a bit.
For example, a divide ratio of 9 if you have 8 ADCs. Now the 2nd ADC's
delay circuit is adjusted until the 9th conversion result is the same as
the 1st, the 3rd ADC's circuit until the 18th result is the same as the
1st, and so on.

Hi,

Thanks for the info, I guess the interleaving is another area that
reduces these high speed scopes sensitivity, since the signal is fed
in parallel to all the interleaved channels, the input impedance isn't
infinite on the inactive inputs, so the impedance of the scope goes down
with interleaving. Maybe there is a plasmonic chip design out there
hat runs synchronous with the ADC sample clock and is like a plasmonic
relay to cut off the inactive ADC's at the right time and increase the
scopes input impedance. Or else some 1THz+ mosfets back to back on each
ADC input to act as input switches, maybe this is already done, it seems
like 8 interleaved channels would reduce the sensitivity of the scope
too much otherwise?

cheers,
Jamie

 

[Joerg]

Hi,

Thanks for the info, I guess the interleaving is another area that
reduces these high speed scopes sensitivity, since the signal is fed
in parallel to all the interleaved channels, the input impedance isn't
infinite on the inactive inputs, so the impedance of the scope goes down
with interleaving. ...

I doubt it. There will be amplifiers and buffers. Aside from the
sensitivity issue there is also the fact that this oscilloscope will not
be exempt from having to pass EMC regulations. An ADC with its input
piped out directly would usually result in guaranteed failure because
the clock spews out. Nowadays it's measured up to 6GHz but even if it
was above, customers would not appreciated if a new piece of equipment
pollutes the RF stuff in their lab.

Maybe there is a plasmonic chip design out there
hat runs synchronous with the ADC sample clock and is like a plasmonic
relay to cut off the inactive ADC's at the right time and increase the
scopes input impedance. Or else some 1THz+ mosfets back to back on each
ADC input to act as input switches, maybe this is already done, it seems
like 8 interleaved channels would reduce the sensitivity of the scope
too much otherwise?

Nah, they are usually run all in parallel. But there are buffers before
each ADC and in front of that another amplifier. In a scope you've got
to, because the input range of a typical ADC is much too wide and a
scope must be able to get down to 20mV/div or less.

There is another reason for buffers. If you hang ADC inputs parallel
they will disturb each other. That can cause auto-calibration routines
in a stagger-scheme to not converge or go bonkers.

 

[Frank Buss]

You usually need to electronically tune the aperture delay. BTDT. Not at
10GHz but "only" 100MHz or so and 12-bits. However, the client didn't
want to see any residual stuff down to -100dB which made this a nice
challenge.

Sounds interesting. How do you get -100dB with 12 bits? Would need at
least 17 bits. A moving average filter could work:

http://www.picotech.com/education/oscilloscopes/resolution-enhancement.html

But I guess for the extra 5 bits you would need 32 times the sample
frequency?

 

[Joerg]

Sounds interesting. How do you get -100dB with 12 bits? Would need at
least 17 bits. A moving average filter could work:

http://www.picotech.com/education/oscilloscopes/resolution-enhancement.html

But I guess for the extra 5 bits you would need 32 times the sample
frequency?

In this case it was Doppler processing. The bandwidth of the information
was much lower than in normal aquisition mode (which was also used) and
then you average over many samples plus over time. How much SNR increase
will result depends mostly on the length of the pulsed Doppler receive
window which is called range gate. The actual gating electronics are
often also called range gate.

For this to work the ADCs need to be super-duper quiet, much more so
than they'd have to be for the normal 12-bit work. This also means that
the phase jitter that such an auto-calibration shifter introduces has to
be as much down as your full averaged SNR.

An example how tough this can be: A client had a noise problem in a
similar system. Just a faint line on the FFT. But it annoyed their end
customers. Before they called me they had tried the most expensive
spectrum analyzers on it but could not find anything. So I showed up
with a receiver and head phones. The only way to find it was with the
receiver switched to singel-sideband reception and slowly turning the
dial through a large swath of frequencies. Because in a Doppler system
everything folds into the spectrum at the pulse repetition frequency,
which makes noise hunting tedious.