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Active PFC multiphase output question

Discussion in 'Electronic Design' started by Scott Ronald, Mar 30, 2008.

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  1. Scott Ronald

    Scott Ronald Guest

    I am looking at a multiple boost converter active power factor
    correction circuit like below:

    vin = 160*|sin(2pi*60*t)|
    input filter is a LC lowpass, with cutoff somewhere between 60Hz and F_PWM

    |-------------[input filter]-|---[inductor1]--|-[diode]-|---|----|
    | | | | | |
    | | [PWM1]--[fet1]-[gnd] | | [load]
    [vin] | | | |
    | |---[inductor2]--|-[diode]-| [cap] |
    | | | | | |
    | | [PWM2]--[fet2]-[gnd] | | |
    | | | | |
    | |---[inductor3]--|-[diode]-| | |
    | | | | | |
    | | [PWM3]--[fet3] | | |
    | | | | | |

    My question is about the PWM controllers. My sampling rate is 100kHz so
    I make my adjustments to the duty cycle at 100kHz.

    should I run the PWMs separately and possibly have overlap so
    in the 10us period:
    PWM1 can be on from 0 to 5us
    PWM2 can be on from 2.5us to 7.5us
    PWM3 can be on from 5us to 10us
    (each PWM has the same duty %)


    A single multiplexed 300kHz PWM so that with no overlap
    in the 10us period:
    PWM1 can be on from 0 to 3.333us
    PWM2 can be on from 3.333us to 6.666us
    PWM3 can be on from 6.666us to 10us
    (each PWM has the same duty%)

  2. Gerhard

    Gerhard Guest


    The duty cycle of each boost converter must vary between almost 100% at the
    zero crossings of the mains voltage and almost zero at the peak of the mains
    voltage, when it is close to the output voltage.
    So, when switching at 100KHz, the gate pulses for each boost FET must vary
    between 0-10us.
    To have optimum benefit (ripple current reduction at the input and the
    output) from the three boost converters, they must be interleaved: the
    pulses must be shifted by 120°, in other words, the leading edge of the
    pulses must be delayed by 3.33us.

    Best regards,

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