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AC Square Wave 10A Power Supply

Discussion in 'Power Electronics' started by LKO Railroad, Jul 25, 2018.

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  1. LKO Railroad

    LKO Railroad

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    Aug 9, 2013
    From a regulated +-15v 10A power supply I need a 8kHz square wave of +-15v 10A 50% duty cycle. Am I on the right track with this circuit? Thank you in advance.
    square_wave_ps.png
     
  2. WHONOES

    WHONOES

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    May 20, 2017
    Yes and No. In simulation, the circuit runs at 8Khz with a capacitor value of 1nF.
    With the transistor configuration that you have shown, both devices will be on during the positive to negative and negative to positive transitions resulting in their destruction.
    You will be better off with a common source arrangement as in a power amplifier output stage.
    The problem then is that you will not achieve the ±15V O/P you want without the gate drive voltages being at least 5V larger than the 15V supplies. Then there is the issue of saturation whereby the current flowing in the transistors causes a voltage drop across each of them. This is determined by the on resistance of the device which, as far as I can see, is about 70mΩ which gives about 700mV drop. That assumes that the transistors are fully enhanced which will probably not occur without around 10V between gate and source.
    Finally, the gate resistors might be a bit large at 1KΩ. Make them as small as you can without the O/P stage oscillating.
     
    LKO Railroad likes this.
  3. LKO Railroad

    LKO Railroad

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    Aug 9, 2013
    Thank you for the response.

    Other issues aside for a moment, would fast series diode on gate solve the transition issue? Adding hysteresis so to speak. A symmetrical output is not extremely critical.

    square_wave_ps2.png
     
    Last edited: Jul 25, 2018
  4. WHONOES

    WHONOES

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    May 20, 2017
    Try the attached circuit. I will leave you to figure out how it works. But if you struggle come back and I will explain.
    Look at the graph in conjunction. It shows a gap between the transitions.
    The circuit allows you to use your original FET configuration.
    Note that the 40106's are cmos devices and can have an absolute maximum supply voltage of 18V though are usually run at upto15V.

    Edit. Just spotted a very minor error on the attached schematic. The output of U3 should go to the output of U2 and not the base of Q2.
     

    Attached Files:

    Last edited: Jul 25, 2018
    LKO Railroad likes this.
  5. LKO Railroad

    LKO Railroad

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    Aug 9, 2013
    Greatly appreciated. Do I understand correctly?

    U1, C1, R1 = oscillator;
    U6 = oscillator inverse;
    D1, D2, R2, R3, C3, C4 = dead band, charge rapid thru D, discharge slow thru R;
    U2, U3, U4, U5 = driver/oscillator isolation;
    R8 = ??? seems it should be series Q2 base?
    R6, R5 = Q1 bias;
    R7, R4 = Q1, Q2 current limit;
    Your circuit @ +15v 0v;
    FET @ +15v 0v, -15v;

    Now there is no need for gate resistors on the FETs, correct?
     
  6. WHONOES

    WHONOES

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    May 20, 2017
    U1, C1, R1. Correct.
    U6 Correct.
    Dead band: Other way round to your assumption (if I have read it correctly). Each half charges through R2 and R3 which gives the required time constant. The discharge is through D1 and D2 which happens on the negative transitions of U1 and U6.
    U2, 3, 4 and 5 are part of the dead band circuit. The 40106 is a Hex Schmitt inverter and provides a nice sharp transition from + to - and back again. It also helps define the time constant as they switch at 70% of the rail voltage for + transition and 30% for a - transition. Therefore the dead band is defined purely by the + transition of each half.
    Incidentally the time constant is literally R2 x C3 where R is in ohms and C is in Farads.
    R6 and R5 are for level shifting for Q1.
    R7 and R4 are to turn you FET's off when either Q1 or Q2 is not conducting.
    Yes, bulk of circuit is intended to work on +15V only hence the level conversion around Q1 for the -15V part.

    I would include gate resistor to ward of any chance of parasitic oscillation in your output stage. 100Ω May be enough or maybe even less. As I said earlier go for the minimum value that gives stable operation.

    The paralleling of U2, U3 and U4, U5 are not strictly necessary it's just that if you didn't, you would have two gates in the package that were doing nothing and would probably sit there and oscillate at very high frequency, draw lost of current and probably interfere with what you are doing so, make them do something useful instead.

    Hope that all makes sense.
     
    LKO Railroad likes this.
  7. LKO Railroad

    LKO Railroad

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    6
    Aug 9, 2013
    Makes complete sense. May I ask again why R8 is connected across U2 and U3 outs instead of series to Q2 base?

    Thank you again for the schematic and answering my questions. I may post one final drawing for your review before I breadboard if that is okay.
     
  8. WHONOES

    WHONOES

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    May 20, 2017
    AS I said in an edit earlier the O/P of U3 should be connected to the O/P of U2. It was a drawing error on my part. R8 should then be in series with the combined U2 and U3 O/P's and the bas of Q2.

    Feel free with the review drawing.
     
  9. LKO Railroad

    LKO Railroad

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    Aug 9, 2013
    I apologize. I missed the edit.
     
  10. WHONOES

    WHONOES

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    May 20, 2017
    Not a problem.
     
  11. WHONOES

    WHONOES

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    May 20, 2017
    I have just remembered that my simulator only does 4000 logic series simulations at 5V. The only things that it may affect is the value of R6 and possibly R8. I would suggest trying R6 at 8K2 and R8 at 3K3.
    I would also advise bread boarding it a stage at a time and check that it works correctly before going onto the next stage and certainly do not connect Fet's until you are happy with the rest of the circuit.
    I hope you have a scope as you will need one to check functionality.
     
    BobK likes this.
  12. LKO Railroad

    LKO Railroad

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    Aug 9, 2013
    I do. It is an ancient Heathkit IO-4530 but it still works great.
     
  13. WHONOES

    WHONOES

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    May 20, 2017
    Good. So long as it works, that's all that matters.
     
  14. LKO Railroad

    LKO Railroad

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    Aug 9, 2013
    Do I have it drawn correctly?

    Clipboard01.jpg


    [mod note: image shown in post rather than as a pdf file]
     
    Last edited by a moderator: Aug 4, 2018
  15. WHONOES

    WHONOES

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    May 20, 2017
    No. The PNP transistor at the bottom is schematically upside down. The 1K collector resistor of the same device should be connected to -15V as should the end of the 10K resistor that currently goes to ground. It would help future de-bugging if you could put indent's on each of the components in your schematic i.e. R1, Q1, C1, IC1a etc.
     
  16. LKO Railroad

    LKO Railroad

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    Aug 9, 2013
    Round 2

    schematic.png
     
  17. WHONOES

    WHONOES

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    May 20, 2017
    Looks OK now. As I said previously, build it up and set to work a section at a time. As I found very early on in my electronics life, building a circuit in one hit is fraught with problems. If it fails t work, where do you start? whereas when doing it a section at a time, if the next bit added stop it working properly, you know which bit to investigate. Finally, don't connect the FETs until you are satisfied the rest of it is working properly.
     
  18. LKO Railroad

    LKO Railroad

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    6
    Aug 9, 2013
    Thank you again.
     
  19. WHONOES

    WHONOES

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    May 20, 2017
    Do let us know how you get on.
     
  20. LKO Railroad

    LKO Railroad

    43
    6
    Aug 9, 2013
    Will do.
     
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