Absolute maximum voltage -- how long can digital chips stand it?

[Bob Boblaw]

How long do digital chips typically last when operated at their
absolute maximum voltage?

How long do they typically last at recommended voltage?

 

[mike]

How long do digital chips typically last when operated at their
absolute maximum voltage?

How long do they typically last at recommended voltage?

Are you sure you understand what you're asking?
There's often a disclaimer in the spec that the device is not
guaranteed to do anything at the absolute maximum voltage except survive.

If you're suggesting that you will operate ANY component at its
absolute maximum voltage, you should inform your employer so they
can fire you before you put them out of business.

 

[Klaus Kragelund]

How long do digital chips typically last when operated at their

absolute maximum voltage?

Typically, no way to say

How long do they typically last at recommended voltage?

Typically, 20 years?

Tests I have made once on a 4000 series CMOS designed for abs max 18V failed at 21V. But that test was highly un-scientific

Regards

Klaus

 

[Bob Boblaw]

Are you sure you understand what you're asking? There's
often a disclaimer in the spec that the device is not
guaranteed to do anything at the absolute maximum voltage
except survive. If you're suggesting that you will operate
ANY component at its absolute maximum voltage, you should
inform your employer so they can fire you before you put
them out of business.

I don't want to run at that voltage. I'm just asking because
others do, and I'm actually trying to talk them out of it.

The chips are DDR3 DRAM recommended for 1.50V or 1.35V and
rated 1.975V absolute maximum. A few retail brands of DDR3
modules are sold with recommended voltages of 1.9V - 2.1V,
those recommendations coming from the module marketers, not
the chip makers, and I just want to know how long they'll
likely last.

 

[Fred Bartoli]

John Larkin a écrit :

We've used some opamps rated at 12 max, and they failed at 12.

Interesting.
Any ref?

 

[Joerg]

Harris, now Intersil, HFA1130 clamp-amps. 11 volts seems OK.

As a student I bought a few expensive Intersil chips for our RF
institute. They were 5V nominal and something like 6V max. They would
not work at all unless they saw at least 6.7V. Called them, was brushed
off rather impolitely, they would not replace them. I never designed in
an Intersil part in my whole career.

 

[Joerg]

The clamp-amps are cute, but they have way too much personality.

I like electronic parts to be more on the disciplined side

Reminds me of an old friend. After a very long military career he
started at an electronics company. Left after a few years. "So you
didn't like the job?" ... "Oh, I did. I just could not stand civilians,
with all their personality issues".

 

[[email protected]]

There's probably no difference.



Failure rates, absent abuse, are measured in FITS, where one FIT is

one failure per billion hours. Digital ICs are usually a few FITS for

simple stuff, numbers like 20 or 100 for an FPGA maybe. Some vendors

will supply numbers if you search around or ask directly.



Reliability does go down as temperature goes up, about 2:1 incease in

FITS per 10 degrees C. So if higher supply voltage makes the chips get

hotter, that could matter.





--



John Larkin Highland Technology, Inc



jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com



Precision electronic instrumentation

Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

VME thermocouple, LVDT, synchro acquisition and simulation

If it's MOS then the most likely failure mechanism is some kind of gate oxide overstress breakdown. Failures won't be measured in FITS then.

 

[miso]

How long do digital chips typically last when operated at their
absolute maximum voltage?

How long do they typically last at recommended voltage?

The answer is "indefinite." I always thought the absmax rating was kind
of stupid since nobody specs the time it will survive. Parts with short
circuit protect often have an indefinite time as well, though short
circuit protection is on a better engineering footing that absmax. That
is a design engineer understands the innards of short circuit
protection, but there can be nuances in stressing devices.

In the ATE characterization program (not to be confused with a test
program), you typically stress a part for a second. Nobody is going to
waste a second of test time for this in real life, i.e production.

Some companies will run the characterization test under normal
conditions, stress the part, then run it again to see if the numbers
change. This is all different from company to company. I've yet to
understand what all this ISO9xxx crap accomplished since quality flow is
not standardized to the best of my knowledge. Or if it is, some
companies go beyond the standard. The ISO standards make you document
what you do, but don't specifically say what to do. [My opinion as
someone who never worked in QA.]

 

[SoothSayer]

Ok, let's take your 1.50V DRAM, and run it at 1.975V. (The 1.35V
variety will be worse). That's 1.32 times the rated voltage. Power
dissipation goes up with the square of the voltage. So, that 1.32^2 =
1.73 times the rated dissipation. The current also goes up
(somewhat). My guess(tm) is it's linear yielding 1.73 * 1.32 = 2.3
times the dissipation of the chip at the rated voltage. Got a heat
sink and fan? You'll need it them.

I don't have any experience with running RAM at maximum voltages.
There's really no benefit. Assuming it doesn't just blow up (which it
probably will anyway), there's the not so minor consideration of error
rate. By running the chips at the extreme voltage, the threshold
voltages for what it considers a one or zero change somewhat. In
theory, if you increase the operating voltage, you also increase the
noise margin. In reality, all you're doing is running the threshold
detectors closer to one rail or the other. You might want to track
the error rate of whatever device you're designing.

DRAM error rates: Nightmare on DIMM street
<http://www.zdnet.com/blog/storage/dram-error-rates-nightmare-on-dimm-street/638>
<http://research.google.com/pubs/pub35162.html>
<http://research.google.com/pubs/archive/35162.pdf>

One would think that the folks who would know would be the makers.

The game overclockers do not always get it right, but I'll bet the
makers have beat the hell out of them all.

So, I'd ask Patriot or Corsair if an overclocked stick works better
with the operating voltage tweaked, left alone or retarded. There are a
number of other RAM 'firing' (reading, writing, refreshing) settings
which can be managed on some motherboards as well.

I think your points are valid, but when we are talking about mere
tenths of volts here, I think the window indeed shifts, but the noise is
nowhere around until one gets outrageous with the voltage tweak.

 

[miso]

I don't have any experience with running RAM at maximum voltages.

There's really no benefit. Assuming it doesn't just blow up (which it
probably will anyway), there's the not so minor consideration of error
rate. By running the chips at the extreme voltage, the threshold
voltages for what it considers a one or zero change somewhat. In
theory, if you increase the operating voltage, you also increase the
noise margin. In reality, all you're doing is running the threshold
detectors closer to one rail or the other. You might want to track
the error rate of whatever device you're designing.

With increased supply voltage, you are fighting stronger "opposing"
devices, so the threshold usually goes up, as in further from the rails.
[The opposite sex device starts at the full supply voltage, so it is at
full strength.] In any event, it is a bad idea to run at elevated voltages.

DRAMs are quite sophisticated these days, employing PLLs and such. Some
have thermal sensors. Why play with fire?

Most of the intel mobos these days use 2x interleaved scheme. The older
mobos were 3x. They made an "extreme" series that was 4x but the
performance wasn't improved at all. In most cases, you are better off
having more ram than less ram at a faster speed.

 

[[email protected]]

Ok, let's take your 1.50V DRAM, and run it at 1.975V. (The 1.35V
variety will be worse). That's 1.32 times the rated voltage. Power
dissipation goes up with the square of the voltage. So, that 1.32^2 =
1.73 times the rated dissipation. The current also goes up
(somewhat). My guess(tm) is it's linear yielding 1.73 * 1.32 = 2.3
times the dissipation of the chip at the rated voltage. Got a heat
sink and fan? You'll need it them.

"Power dissipation goes up as the square of voltage" and "current goes
up (somewhat)" is double-counting the increase. P~CfV^2.

<...>

 

[rickman]

With increased supply voltage, you are fighting stronger "opposing"
devices, so the threshold usually goes up, as in further from the rails.
[The opposite sex device starts at the full supply voltage, so it is at
full strength.] In any event, it is a bad idea to run at elevated voltages.

DRAMs are quite sophisticated these days, employing PLLs and such. Some
have thermal sensors. Why play with fire?

Most of the intel mobos these days use 2x interleaved scheme. The older
mobos were 3x. They made an "extreme" series that was 4x but the
performance wasn't improved at all. In most cases, you are better off
having more ram than less ram at a faster speed.

The DRAM tester I have is out of date, but a lot of memory failed
when tested at just 3% above nominal.

I don't recall seeing any DRAM devices that weren't spec'd for Vdd of
±5%. Technically these devices were failing if your tester was accurate.

Rick

 

[rickman]

As a student I bought a few expensive Intersil chips for our RF
institute. They were 5V nominal and something like 6V max. They would
not work at all unless they saw at least 6.7V. Called them, was brushed
off rather impolitely, they would not replace them. I never designed in
an Intersil part in my whole career.

I've never been overly impressed with Intersil as a company. There is
certainly no reason for rude support.

I've worked places where getting a $5 PO through channels was a major
PITA so I would ask for samples of nearly everything on the board. When
I asked Intersil for a sample of a 4000 series CMOS part they responded
that they don't sample those parts, they are well understood. I guess
the effort on their part to sample the device was more than the effort
on my part to get a PO though channels. So I didn't use the part. No
big loss on either side.

On the other hand, some sales folks understand the value of getting a
part in the door at companies. Some companies make parts available in
the schematic capture data base which can make things easier for
engineers. This leads to those parts being designed in more often. So
getting a part into a prototype can lead to sales even if that project
doesn't use it in the end.

Rick

 

[rickman]

There's probably no difference.

Failure rates, absent abuse, are measured in FITS, where one FIT is
one failure per billion hours. Digital ICs are usually a few FITS for
simple stuff, numbers like 20 or 100 for an FPGA maybe. Some vendors
will supply numbers if you search around or ask directly.

Reliability does go down as temperature goes up, about 2:1 incease in
FITS per 10 degrees C. So if higher supply voltage makes the chips get
hotter, that could matter.

I've always wondered about that relationship, I seem to recall it is
based on the Arrhenius equation. The basic Arrhenius equation has two
arbitrary constants, one for the activation energy and one for the basic
rate. The exponential describes how the rate varies with temperature.
I find it odd when equations work out to nice round integers like 2:1
and 10°C. That makes me think this is a vast simplification and is very
approximate, mostly used because it is convenient and "close enough".

Anyone know what the basis for this relationship is? I think I looked
it up once and didn't find a real basis for it. There is no physical
basis for 10°C so I expect it is all very arbitrary and actually varies
a lot in the real world. Or is there something basic I am missing?

Rick

 

[rickman]

I've yet to
understand what all this ISO9xxx crap accomplished since quality flow is
not standardized to the best of my knowledge. Or if it is, some
companies go beyond the standard. The ISO standards make you document
what you do, but don't specifically say what to do. [My opinion as
someone who never worked in QA.]

You are absolutely right. ISO9000 is more about being able to explain
and justify what you are doing rather than making sure you are doing it
right. There is lots of benefit in that. I was hired by one company
who had hired more engineers in the past year than they had from prior
to that. How do the new hires know how the company is to function? I
don't recall if engineering was ISO9000, technically they were a DOD
outfit and they were just getting their CMMI certification, which is
much similar. In many ways CMMI training is a joke. The CMMI
instructors know the "rules" for CMMI, but can't tell you anything about
how to apply them to your process. In this case we all flailed about
and did a lot of talking in circles. The worst part was in the first
bid I worked on we were adding time to the schedule to make the CMMI
stuff happen and it infuriated the head guy. "If it doesn't save us
time and effort, why are we doing it?" That was a valid point so all
the scheduled time for doing the CMMI stuff was removed along with a
bunch of other fat.

In many ways this company was using the infinite monkey process... but
they did manage to get product out the door. Some of the factory people
were pretty good, but some of them hated engineers. Too bad, I like
working with manufacturing. No point in designing a product only to
have it be hard to make.

Rick

 

[miso]

"Power dissipation goes up as the square of voltage" and "current goes
up (somewhat)" is double-counting the increase. P~CfV^2.

<...>

The P=CfV^2 equation is based on shoveling buckets of charge at a given
rate. But the shoot through aka crowbar current will go up with supply
voltage. I'm reading Jeff's mind here, assuming that was what he meant.

There is a lot more than just logic to RAM design. PLLs, sense amps
etc,so the bucket of charge back of the envelope equation that works for
basic logic might not be operable for a DRAM.

 

[Bob Boblaw]

One would think that the folks who would know would be the makers.

The game overclockers do not always get it right, but I'll bet the
makers have beat the hell out of them all.

I don't think they test thoroughly but mostly use just PCs, and one
company even admitted allowing up to 2 bad bits in final testing. Almost
all retail modules are made with no-name or overclocked chips under their
purely decorative heatsinks, like these 2133 MHz G.Skills containing
Hynix H9 (1333 MHz) speed grade chips (pictures):

http://aphnetworks.com/reviews/g_skill_ripjaws_x_f3_17000cl9d_8gbxld_2x4gb/2

10% of similar modules have failed on me, compared to 0% for modules
made with brand name chips not overclocked.

 

[[email protected]]

I don't think they test thoroughly but mostly use just PCs, and one
company even admitted allowing up to 2 bad bits in final testing. Almost
all retail modules are made with no-name or overclocked chips under their
purely decorative heatsinks, like these 2133 MHz G.Skills containing
Hynix H9 (1333 MHz) speed grade chips (pictures):

http://aphnetworks.com/reviews/g_skill_ripjaws_x_f3_17000cl9d_8gbxld_2x4gb/2

10% of similar modules have failed on me, compared to 0% for modules
made with brand name chips not overclocked.

Funny, I ordered three sticks of memory from Crucial (Micron) recently
- one dead. I didn't think the 33% fallout, from the horse's mouth, to
be very good either.

 

[[email protected]]

The P=CfV^2 equation is based on shoveling buckets of charge at a given
rate. But the shoot through aka crowbar current will go up with supply
voltage. I'm reading Jeff's mind here, assuming that was what he meant.

Shoot-thru looks like another capacitor; also proportional to f
(number of transitions) and V^2 (impedance of the output devices).

There is a lot more than just logic to RAM design. PLLs, sense amps
etc,so the bucket of charge back of the envelope equation that works for
basic logic might not be operable for a DRAM.

Also proportional to f and V^2. I don't see a V^3 component yet.