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About the subthreshold swing in SOI CMOS

Discussion in 'Electronic Design' started by Schmit, Apr 20, 2006.

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  1. Schmit

    Schmit Guest

    For fully depleted SOI, some book says it can reach a nearly 60mV/Dec
    swing because its effective gate depletion width is large. What does
    "effective gate depletion width" mean ? I have only heard of "depletion
    width" in a bulk CMOS. Is it a unique advantage of SOI ? I am
    suspicious about it. If the depletion width (Wd) of bulk CMOS can be
    made big enough, then the control coefficient m=1+3tox/Wd also can
    approach 1.
    Thanks for attention
     
  2. Guest

  3. Schmit

    Schmit Guest

    I think I got the answer.
    Thanks a lot.
     
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