Connect with us

A 1.5V to (1.5V -> 6.5V) level shifter, and vice versa

Discussion in 'Electronic Components' started by alan, Oct 1, 2007.

Scroll to continue with content
  1. alan

    alan Guest

    Basically, my boss wants me to build a testing system for an IC, which
    has an absolute maximum rating of 1.5V to 6.5V VCC.

    So my boss wants me to apply some digital signals to the IC and read
    some feedback (at up to 20MHz clock). With a variable VCC from 1.5V
    to 6.5V (and other features besides, such as being low power). And I
    need to be able to apply 1.5V to 6.5V voltage at high, based on my
    current VCC.

    However the only level shifters I've found are either 1.5V to 5.5V
    supply voltages or 4V to very high supply voltages. Nothing quite
    fits the 1.5V to 6.5V range.

    The best I've managed to come up with is to use a bunch of
    (mechanical) relays to select between two level shifters, one for 1.5V
    to 5.5V range, the other for 5.5V to 6.5V range. I'm not sure if
    solid-state relays will work, because I'm almost sure that the
    propagation delay of actual metal is much faster than propagation
    delay of semiconductor.

    Is this the best solution? Might I have missed a level shifter
    capable of reaching the required range?

    My controlling device is an FPGA, which can have a VOH of 1.2V, 1.5V,
    3.0V and 3.3V (1.5V and 3.3V being the preferred, because our FPGA
    prototyping board has only those voltages). The maximum recommended
    VIH for the FPGA is 4.1V, with the minimum obviously varying according
    to the I/O VCC I select.

    Thanks in advance!
     
  2. -----BEGIN PGP SIGNED MESSAGE-----
    Hash: SHA1
    I would suggest you use the 1.5v boost converter and a 4.7v zener to
    limit the voltage.

    - --
    Brendan Gillatt
    brendan {at} brendangillatt {dot} co {dot} uk
    http://www.brendangillatt.co.uk
    PGP Key: http://pgp.mit.edu:11371/pks/lookup?op=get&search=0xBACD7433
    -----BEGIN PGP SIGNATURE-----
    Version: GnuPG v1.4.3 (MingW32)

    iD8DBQFHAQk3kA9dCbrNdDMRAq+iAKDf98JQLfUMl7ZhTOQ1J+jOvCN52gCgq3vQ
    tQFzVUNYCRktYNPlDVh5Q1k=
    =PzFr
    -----END PGP SIGNATURE-----
     
  3. Sometimes an input might be driven with a voltage reaching or exceeding the
    supply voltage, If you have to test this condition, you need two variables,
    your supply, and your pullup voltage.

    Once you have those it's easy with the method I copy from an old post of
    mine (idea raided from a 'Best of EDN' book I found).

    Try an n-channel JFET, gate to common ground, pull-up voltage through
    resistor on the drain, input to the source. Anything over 1 to 2V input
    should be fine. Without having seen your circuit I can't be sure, but this
    might all be doable with a single FET per input. I'm not sure how low your
    pullup voltage can go but if the FET is satisfied, you could offset the
    final voltage the inputs see by passing through one or more signal diodes
    between FET drain and input. You'd then have a continuously variable range
    to test by adjusting the main pullup supplie's voltage.
     
  4. Note to self: If I ever make a typo that tasteless again I'll shoot myself,
    I swear. >:)
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-