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80c186 and transparent latch?

Discussion in 'Electronic Design' started by Mook Johnson, Aug 27, 2005.

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  1. Mook Johnson

    Mook Johnson Guest

    I'm working on a design that uses an 80c186 with external memory and rom.

    While diagnosing i realized something that is strange to an analog inclined
    person like myself. The bus is multiplexed using a transparent latch which
    makes the the outputs follow the inputs while the LE is high (transparent
    part) and latched in the falling edge. (old 373 chip). What I didn't
    expect to see was that the AD signals change while the 80c186 ALE is high
    and therefore cause glitches on the output of the latch (address bus). The
    system works because the setup and hold times for the memories are not
    violeted before the read/reite signals are asserted, but it would seem to
    add to the EMI produced by the memory bus. This would be solved if the
    address was only latched on the negative edge without the transparerent part
    when LE is high.

    Am I missing something here?
     
  2. Tam/WB2TT

    Tam/WB2TT Guest

    Sort of. The way it is set up gives you the most address setup time. That
    is, address on the buffered bus is valid long before the falling edge of
    ALE. Keep in mind, though, that when the original 186 came out, memory was
    slow. By using an edge triggered latch, you are also changing the address to
    READ and WR times.

    BTW, congratulations for using a 373 and not the stupid Intel part. I would
    use the HCT, though.

    Tam

    Tam
     
  3. Mook Johnson

    Mook Johnson Guest

    Thanks I knew there had to be a reason.

    The word "tranparent" was lost on me and I thought the latch was bad because
    the output was changing "before" the falling edge Turned out this is
    correct behavior but lead to this topic as to why this is desirable.

    thanks again
     
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