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8051F020 series, 5V tolerant input schematic?

J

Joerg

Jan 1, 1970
0
John said:
Jim said:
Jim Thompson wrote:
Jim Thompson wrote:
Jim Thompson wrote: [...]


And Analog Devices modeling efforts are now managed by a MARKETING VP,
and they are ultimately heading to requiring simulation of their parts
ONLY on their web-based simulator.

That would be a marketing decision that borders on stupid.
I was there (San Jose) last August trying to convince them of the best
way to do modeling... let me see the real netlist and then I'd match
it behaviorally. The MARKETING VP nixed the idea.

(I even showed them various posts from this newsgroup complaining
about model quality... did no good.)

Then I assume they'll never understand why, when it comes to performance
and cost is not a major issue, I always default to LTC and never even
look at AD unless I can't find a chip at LTC. This is because LTC has
behavioral models that work in LTSpice and AD does not.

Same with TI. Who in their right mind would install and learn half a
dozen competing "free" simulators? If they can't understand that LTSpice
is the de facto winner, oh well.
PSpice will run ANY non-encrypted model, as will LTspice, HSpice, any
Cadence tool, and most amateur spin-offs.

If you run a complicated switcher non-behavioral (and I had to do that)
the sims take forever. For designing SMPS that clearly is not the most
efficient method.


Encrypting so a model will run only on the parent tool turns me off.
Me, too.


What do you do if you want to mix LT and ADI and TI parts on your
board? You're screwed.

On high end designs I never do that, and there is no need to. You can
usually get everything at LTC. Except for some hardcore RF stuff and
then that gets simulated separately.

If it has to be cheap then no special ICs are used anyhow most of the
time. For example, my first mass-produced device with a boost converter
revolves around a CD40106 as the "highest-tech" chip. There is no
dedicated PWM chip because that would have added at least 10c back in
the early 90's.


Joerg, sounds like LT is happy as a clam with you. You're a locked-in
customer. Enjoy >:-}

Well, yeah, at some point you have to pick one and run with that. I have
made my choice, and that choice is LTC.
"Most" of their stuff is good. I've had a recent situation where an
encrypted model works just fine on LTspice, but not on a PCB.
Same here, the LT6700 had a glitch on the chip and I was the unfortunate
one who had to discover that the hard way.

The FAE was flummoxed, referred the problem to factory... 4 months
have passed, no solution.
In my case the LTC design engineers looked at it right away, found out
that it was indeed a bug, fessed up, apologized, rolled up the sleeves
and corrected things. That left a very positive impression with me.

Over the years I experienced numerous similar situations with other,
larger manufacturers. The classic solution was an attempt to cover it up.

I posted the problem on the LTspice list, but was basically told,
"LTspice, love it or leave it" :-(

All I've been able to find out is that LTspice encrypted models are
behavioral internally.
They are, mostly. That is the reason why you can simulate switchers so
blazingly fast. This does come with pitfalls and (minor) risks but it
sure beats non-behavioral sims that take hours.

My LT3757 boost sim runs at about 15 PPM of real time. I need seconds
of sim to model my product, so I'd get two or three runs per week. And
I'd run out of hard drive for the RAW file!

If it's not super secret send it over and I'll take a look. There's
usually a way to speed things up, like by pre-charging a large cap and
things like that.

I've ordered samples.

It's a good chip, I don't think you'll be disappointed.
 
J

Joerg

Jan 1, 1970
0
John said:
[...]
Look thru the HELP for "alternate solver"... some types of parts
require a different matrix parsing.

...Jim Thompson

If I improved it 20:1 it would still be too slow to give me useful
feedback, and I'd still run out of hard drive. I was getting 10G RAW
files from milliseconds of sim time.

And I don't entirely trust the simulation; sometimes it does weird
double or staggered gate drive pulses that don't make obvious sense.

Besides, it's fun to solder stuff now and then.

When a chip like the LT3757 isn't maxed out in frequency and gate
capacitance load I usually provide an 0.080" via underneath. Mostly
without thermal relief to the plane. That way I can reach in with a
Weller ETS tip to get it off the board.
 
On Wednesday, June 26, 2013 12:39:43 PM UTC-4, Joerg wrote:


Clamping makes no sense for logic families designed to operate off a wide range of power supplies and able to withstand being mixed up with logic operating off different supplies. Your thinking is very 1970ish. Nothing wrong with the architecture, it is used in some extremely fast logic families, ithas been perfected IOW. Finally, the modern gate oxide process does not blow a hole instantaneously when the voltage stress exceeds some threshold byone microvolt. It is a graded breakdown that requires time.
 
J

Joerg

Jan 1, 1970
0
John said:
John said:
Jim Thompson wrote:
Jim Thompson wrote:
Jim Thompson wrote:
Jim Thompson wrote:
[...]


And Analog Devices modeling efforts are now managed by a MARKETING VP,
and they are ultimately heading to requiring simulation of their parts
ONLY on their web-based simulator.

That would be a marketing decision that borders on stupid.
I was there (San Jose) last August trying to convince them of the best
way to do modeling... let me see the real netlist and then I'd match
it behaviorally. The MARKETING VP nixed the idea.

(I even showed them various posts from this newsgroup complaining
about model quality... did no good.)

Then I assume they'll never understand why, when it comes to performance
and cost is not a major issue, I always default to LTC and never even
look at AD unless I can't find a chip at LTC. This is because LTC has
behavioral models that work in LTSpice and AD does not.

Same with TI. Who in their right mind would install and learn half a
dozen competing "free" simulators? If they can't understand that LTSpice
is the de facto winner, oh well.
PSpice will run ANY non-encrypted model, as will LTspice, HSpice, any
Cadence tool, and most amateur spin-offs.

If you run a complicated switcher non-behavioral (and I had to do that)
the sims take forever. For designing SMPS that clearly is not the most
efficient method.


Encrypting so a model will run only on the parent tool turns me off.
Me, too.


What do you do if you want to mix LT and ADI and TI parts on your
board? You're screwed.

On high end designs I never do that, and there is no need to. You can
usually get everything at LTC. Except for some hardcore RF stuff and
then that gets simulated separately.

If it has to be cheap then no special ICs are used anyhow most of the
time. For example, my first mass-produced device with a boost converter
revolves around a CD40106 as the "highest-tech" chip. There is no
dedicated PWM chip because that would have added at least 10c back in
the early 90's.


Joerg, sounds like LT is happy as a clam with you. You're a locked-in
customer. Enjoy >:-}

Well, yeah, at some point you have to pick one and run with that. I have
made my choice, and that choice is LTC.
"Most" of their stuff is good. I've had a recent situation where an
encrypted model works just fine on LTspice, but not on a PCB.

Same here, the LT6700 had a glitch on the chip and I was the unfortunate
one who had to discover that the hard way.


The FAE was flummoxed, referred the problem to factory... 4 months
have passed, no solution.

In my case the LTC design engineers looked at it right away, found out
that it was indeed a bug, fessed up, apologized, rolled up the sleeves
and corrected things. That left a very positive impression with me.

Over the years I experienced numerous similar situations with other,
larger manufacturers. The classic solution was an attempt to cover it up.


I posted the problem on the LTspice list, but was basically told,
"LTspice, love it or leave it" :-(

All I've been able to find out is that LTspice encrypted models are
behavioral internally.

They are, mostly. That is the reason why you can simulate switchers so
blazingly fast. This does come with pitfalls and (minor) risks but it
sure beats non-behavioral sims that take hours.
My LT3757 boost sim runs at about 15 PPM of real time. I need seconds
of sim to model my product, so I'd get two or three runs per week. And
I'd run out of hard drive for the RAW file!
If it's not super secret send it over and I'll take a look. There's
usually a way to speed things up, like by pre-charging a large cap and
things like that.


No secret, here it is. But C1 needs to be 4000 uF in real life, and I
want to see how it ramps up and stabilizes, and how it recovers after
a big load pulse. I'm making 10G RAW files in milliseconds of sim
time, and I need seconds.

But if you know of any tweaks that would speed it up, I'd appreciate
that.

I don't see much of a point in doing that. The switcher can deliver a
certain amount of energy per cycle, mainly set per R5 and V2. So for
long term sims you could just assume a current source that's curbed when
the regulated output voltage is reached.

If you absolutely have to simulate with 4000uF you could set the
inductor coupling to k=1 which helps a little, then play with abstol and
reltol. But it'll still take forever. 4000uF is huge. Like modeling rear
axle shock response for one complete Sahara desert crossing.
 
J

Joerg

Jan 1, 1970
0
On Wednesday, June 26, 2013 12:39:43 PM UTC-4, Joerg wrote:


Clamping makes no sense for logic families designed to operate off a
wide range of power supplies and able to withstand being mixed up
with logic operating off different supplies. Your thinking is very
1970ish. Nothing wrong with the architecture, it is used in some
extremely fast logic families, it has been perfected IOW. Finally,
the modern gate oxide process does not blow a hole instantaneously
when the voltage stress exceeds some threshold by one microvolt. It
is a graded breakdown that requires time.


The last sentence sums it up what is missing: How many volts above abs
max are allowed over how many milliseconds or microseconds? There use to
be family specs and stuff like that but not anymore.
 
J

Joerg

Jan 1, 1970
0
John said:
[...]

I don't see much of a point in doing that. The switcher can deliver a
certain amount of energy per cycle, mainly set per R5 and V2. So for
long term sims you could just assume a current source that's curbed when
the regulated output voltage is reached.

With all the cap load that I can stand to sim, it actually bursts.
That is probably good in my application.

It does run at about 300 KHz, which isn't what I expected, given the
timing resistor. Maybe, with the inductor I have, it's skipping clocks
waiting for the current to build up to the peak trip point. OK, go
ahead, force me to buy a smaller, cheaper inductor.

That is because the comp node (Vc) initially rails. Once the converter
reaches regulations and Vc comes off its peg it goes slightly above
1MHz, like the datasheet says.

Mantis and Metcal next!

Que quieres decir con eso?

I thought the Mantis is fixed, and the illumination ring gloweth again.
I've always liked the tower-look of Metcals but they are just too durn
expensive for my taste.
 
J

josephkk

Jan 1, 1970
0
Yes, it is, that's what I wrote in the original post :)

The uC has only a 3.3V supply, no 5V supply. But some lines coming in
are from logic that is on 5V, so can't be ESD-clamped lower than 5V.

Well, Jeorg you could use two stage protection; say 50 ohms then a 5.6 V
zener to ground, then another 100 ohms and a 5.1 or even 4.7 volt zener
to ground. Either way, you have to decide.

?-)
 
J

Joerg

Jan 1, 1970
0
josephkk said:
Well, Jeorg you could use two stage protection; say 50 ohms then a 5.6 V
zener to ground, then another 100 ohms and a 5.1 or even 4.7 volt zener
to ground. Either way, you have to decide.

Way too little room for that, otherwise we'd have clamped them all
through intermediate 3.3V rail diodes. It's one of those super-tight boards.
 
J

JW

Jan 1, 1970
0
Joerg said:
Way too little room for that, otherwise we'd have clamped them all
through intermediate 3.3V rail diodes. It's one of those super-tight
boards.

How do you end up in that position? Is there no way to increase the size of
the board when it gets over 90% or so? It is very difficult to route a
tightly-packed pcb, so it costs more.

Is the enclosure the limiting factor? If so, is it possible to split the
board in two and double the available space? This would increase the chance
of coming up with and new idea that could vastly increase the value of the
product. But when your mind knows a pcb is 99% full, you automatically
discard any new ideas because there is no room.

I am amazed at the number of times you and JL mention you cannot use some
solution to a problem because there is not enough room.
 
J

josephkk

Jan 1, 1970
0
Way too little room for that, otherwise we'd have clamped them all
through intermediate 3.3V rail diodes. It's one of those super-tight boards.

Perhaps you need to tell them to give you the space you need or got h***.

?-)
 
J

Joerg

Jan 1, 1970
0
JW said:
How do you end up in that position? ...


Usually through the telephone, "Yo, George, can you help us get this
through cert?".

... Is there no way to increase the size of
the board when it gets over 90% or so? ...


Absolutamente no :-(

... It is very difficult to route a tightly-packed pcb, so it costs more.

Is the enclosure the limiting factor? If so, is it possible to split the
board in two and double the available space? This would increase the chance
of coming up with and new idea that could vastly increase the value of the
product. But when your mind knows a pcb is 99% full, you automatically
discard any new ideas because there is no room.

No chance, it's an existing and very tight unit. Sometimes they have to
be that way, earlier this year I designed something similar but way
different market. Even when dropping to 0402 it barely fit.

I am amazed at the number of times you and JL mention you cannot use some
solution to a problem because there is not enough room.

Comes with the nature of our turf. I design a lot of sensor stuff and
that has to live in crammed quarters. Same for aerospace, there you
typically get told "We have this much volume, here are the dimensions,
and we need something that is xx percent better than what the
competition has".

Think about it like a retrofit market. For example, if you designed a
new fancy timer/dimmer/whatever, it would still have to fit in the
standard North American NEMA box. If it didn't you could not sell it.
Now multiply that by 0.1 :)
 
J

Joerg

Jan 1, 1970
0
josephkk said:
Perhaps you need to tell them to give you the space you need or got h***.

Not sure what the last word should mean but no, this is a normal
situation. I see things like that several times a year.
 
J

JW

Jan 1, 1970
0
Joerg said:
Comes with the nature of our turf. I design a lot of sensor stuff and
that has to live in crammed quarters. Same for aerospace, there you
typically get told "We have this much volume, here are the dimensions,
and we need something that is xx percent better than what the
competition has".

Think about it like a retrofit market. For example, if you designed a
new fancy timer/dimmer/whatever, it would still have to fit in the
standard North American NEMA box. If it didn't you could not sell it.
Now multiply that by 0.1 :)

Very good answer. Thanks!
 
N

Nico Coesel

Jan 1, 1970
0
Joerg said:
Way too little room for that, otherwise we'd have clamped them all
through intermediate 3.3V rail diodes. It's one of those super-tight boards.

I've moved away from diodes to the rail. Many regulators can't sink
current and there is always chance on injecting noise into the supply
lines.

I've used these low leakage zener diodes to improve a design recently:
http://www.nxp.com/documents/data_sheet/BZB984_SERIES.pdf
 
J

Joerg

Jan 1, 1970
0
Nico said:
I've moved away from diodes to the rail. Many regulators can't sink
current and there is always chance on injecting noise into the supply
lines.

You need a shunt that kicks in if the rail wants to ride up. Only an
issue if the total load on the rail has phases where it is very light.
Noise isn't an issue because there is usually lots of capacitance on a
rail and the diodes are only for major ESD events and such.

I've used these low leakage zener diodes to improve a design recently:
http://www.nxp.com/documents/data_sheet/BZB984_SERIES.pdf

Zeners are nice but for many digital circuits the 5% tolerance is too
much. Like the 5V6 in the datasheet which at 5mA can be anywhere between
5.2V and 6V. The datasheet is a bit skimpy, doesn't say what happens if
a pulse of half an amp comes along. Will it go to 7V? More? Probably a
lot more when looking at the differential resistance at 5mA.
 
J

Jasen Betts

Jan 1, 1970
0
Ok, but in real life that's almost unprotectable. The way I usually do
it, there is a diode against the 5V rail, followed by a resistor, then
the port pin. If the pulse from hell comes along that diode can briefly
lean in so badly that Vf goes slightly above 2V, meaning over 7V total.
Bigger diodes aren't an option because that messes up the signal, on
account of their large capacitance.

How about this: series resistor, shunt diode to 3.3V , port pin
 
J

Joerg

Jan 1, 1970
0
Jasen said:
How about this: series resistor, shunt diode to 3.3V , port pin

That doesn't protect very well because the parasitic substrate diode
will take a substantial portion of the hit. The only thing that works is:

R1 -> shunt diodes -> R2 -> port pin.

R2 can be small because there will only be 1-2V max across it and it
only has to make sure the substrate diode gets no more than a few mA.

But ... too many parts in this case.
 
J

Joerg

Jan 1, 1970
0
Joerg said:
That doesn't protect very well because the parasitic substrate diode
will take a substantial portion of the hit. The only thing that works is:

R1 -> shunt diodes -> R2 -> port pin.

R2 can be small because there will only be 1-2V max across it and it
only has to make sure the substrate diode gets no more than a few mA.

But ... too many parts in this case.

Oops, sorry, your are right. At a 5V-tolerant pin it would work. Problem
is that we only have 5V in the area where the protectors are.
 
J

Joerg

Jan 1, 1970
0
Jim said:
If you only have 5V around driving a 5V-tolerant pin... what are you
fretting over?

The concern are surge events that make these lines carry nasty
transients, which in turn can lock up or damage the uC.
 
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