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8051F020 series, 5V tolerant input schematic?

J

Joerg

Jan 1, 1970
0
Folks,

Got a Silicon Labs 8051Fxxx with 5V-tolerant ports. In the abs max it
says 5.8V is the limit. Well, if one uses the typical diode against the
5V rail it could go slightly above 6V in case of a really big jolt.
Since this 8051 does not have a 5V supply but just VDD (which hangs on
3.3V in this case) there can't be any parasitic substrate diodes dumping
into a rail.

Does anyone know the innards? Poly resistors? As usual, the datasheet is
silent about this.
 
L

Lasse Langwadt Christensen

Jan 1, 1970
0
Folks,



Got a Silicon Labs 8051Fxxx with 5V-tolerant ports. In the abs max it

says 5.8V is the limit. Well, if one uses the typical diode against the

5V rail it could go slightly above 6V in case of a really big jolt.

Since this 8051 does not have a 5V supply but just VDD (which hangs on

3.3V in this case) there can't be any parasitic substrate diodes dumping

into a rail.



Does anyone know the innards? Poly resistors? As usual, the datasheet is

silent about this.

from the datasheet the old Virtex fpgas had a "zener like structure to ground"
for 5V pci compliance

I just looked at a STM32 to see if there was anything about the 5V tolerance
in the datasheet

it doesn't say how but it allows Vdd+4V input on 5V tolerant pins, max +0/-5mA injected

normal IO is 4V and +5/-5mA

-Lasse
 
S

Spehro Pefhany

Jan 1, 1970
0
Folks,

Got a Silicon Labs 8051Fxxx with 5V-tolerant ports. In the abs max it
says 5.8V is the limit. Well, if one uses the typical diode against the
5V rail it could go slightly above 6V in case of a really big jolt.
Since this 8051 does not have a 5V supply but just VDD (which hangs on
3.3V in this case) there can't be any parasitic substrate diodes dumping
into a rail.

Does anyone know the innards? Poly resistors? As usual, the datasheet is
silent about this.

According to Xilinx, 5V tolerant pins can add a dozen or so components
per pin. Probably, as Lasse says, it behaves something like a zener
for inputs.

If it's programmable as an output too, they have to add some parts to
keep current from flowing back through the off p-channel.

I don't think you'll find real schematics openly available for this
stuff- on-chip ESD protection seems to be kind of a trade secret.
 
J

Joerg

Jan 1, 1970
0
Spehro said:
According to Xilinx, 5V tolerant pins can add a dozen or so components
per pin. Probably, as Lasse says, it behaves something like a zener
for inputs.


That would be ok but they should state a max peak current. Yet nothing
is stated.

If it's programmable as an output too, they have to add some parts to
keep current from flowing back through the off p-channel.

They are only input-tolerant, they can't output 5V.

I don't think you'll find real schematics openly available for this
stuff- on-chip ESD protection seems to be kind of a trade secret.

Yeah, that was only available in the good old days. "Modern" datasheets
leave a lot to be desired when it comes to hardware details.
 
S

Spehro Pefhany

Jan 1, 1970
0
That would be ok but they should state a max peak current. Yet nothing
is stated.

I guess they assume you'll never exceed the absolute maximum voltage
limits of +5.8/-0.3, so no significant current will ever flow.
 
J

Joerg

Jan 1, 1970
0
Jim said:
"5V-tolerant" pins function by disconnect, not by clamping (somewhat
like the schemes used in hi-Z when unpowered bus devices). The
voltage limit is determined by oxide breakdown.

So you mean like a linear regulator? Because a hard disconnect would
cause the uC to read this pin wrongly, and it reads it correctly. Or do
you mean it disconnects somewhere above 5V?

If they say 5.8V, what's you gut feel it could really take if a surge or
pulse salvo of a few msec comes through? It's amplitude would be
slightly over 7V. because it leans into protective diodes we have up
front of the uC port. Those are regular Si-diodes against the 5V rail
and GND.
 
J

Joerg

Jan 1, 1970
0
Spehro said:
I guess they assume you'll never exceed the absolute maximum voltage
limits of +5.8/-0.3, so no significant current will ever flow.

Ok, but in real life that's almost unprotectable. The way I usually do
it, there is a diode against the 5V rail, followed by a resistor, then
the port pin. If the pulse from hell comes along that diode can briefly
lean in so badly that Vf goes slightly above 2V, meaning over 7V total.
Bigger diodes aren't an option because that messes up the signal, on
account of their large capacitance.
 
You're still fixated on clamping, which would make no sense whatsoever in a mixed signal low power digital environment. The high voltage tolerant inputs are a variation of the theme shown below in one form or another. Operation is self-explanatory:
Please view in a fixed-width font such as Courier.

..
..
..
.. EX High Voltage Tolerant Input
..
..
..
.. VDD
.. | PMOS keeper
.. -
.. ||
.. ||o----------.
.. VDD _|| |
.. | | |
.. | G | |
.. input ___ | | \ | | \ pad
.. pad ___ | | \ | | \ to core
.. _ D | | S | | \ | | \ _
.. |_| ------ ----+-----| o --+---| o----|_|
.. | / | /
.. series | / | / buffer
.. NMOS | / Schmitt | / CMOS
..
..
 
J

Joerg

Jan 1, 1970
0
Jim said:
5V-tolerant INPUTS have no ESD diode to local VDD, just a "snap" diode
to ground. Thus only the input stage gate oxide has to stand-off the
5V.

5V-tolerant OUTPUTS, that is outputs which also serve as INPUTS
(bi-directional bus I/O, etc.) use a disconnect above local VDD.
Visualize the dual series device with "body" at midpoint, that I've
shown here before as a battery-charge control device.

It's all I/O, since it's a 8051-family uC with regular cofigurable ports.


That would work, provided the comparator is past, has little or no
hysteresis and the FETs are snappy. Because the signal integrity of an
incoming 5V data stream must be maintained to full spec'd speed.

DC over-voltage is a no-no... ESD only.

DC will never exceed 5V and abs max is 5.8V. So you think ESD or surges
(the usual machine-gun style bursts in EMC tests) are ok? We have it
clamped to a 5V rail but it could really lean into those clamp diodes.
 
M

Michael Karas

Jan 1, 1970
0
[This followup was posted to sci.electronics.design and a copy was sent
to the cited author.]
This thread rattles around avoiding specifics. Is the "5V-tolerant"
input an input that has 3.3V as VDD?

Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the
I/O Rail VDD. These pins default to typical 8051 style with quasi-
bidirectional behavior with onboard pullup circuitry. The port pins can
also be programmed to be output driven by a totem pole output to the VDD
rail.
 
S

Spehro Pefhany

Jan 1, 1970
0
[This followup was posted to sci.electronics.design and a copy was sent
to the cited author.]
This thread rattles around avoiding specifics. Is the "5V-tolerant"
input an input that has 3.3V as VDD?

Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the
I/O Rail VDD. These pins default to typical 8051 style with quasi-
bidirectional behavior with onboard pullup circuitry. The port pins can
also be programmed to be output driven by a totem pole output to the VDD
rail.

I'd (thankfully) almost forgotten about those miserable quasi
bi-directional port pins.

The schematic on page 161 does not appear to show the brief hard
(~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s
have. If it's present it would be back of the ESD circuitry anyway.

https://www.silabs.com/Support Documents/TechnicalDocs/C8051F02x.pdf
 
J

Joerg

Jan 1, 1970
0
Jim said:
This thread rattles around avoiding specifics. Is the "5V-tolerant"
input an input that has 3.3V as VDD?

Yes, it is, that's what I wrote in the original post :)

The uC has only a 3.3V supply, no 5V supply. But some lines coming in
are from logic that is on 5V, so can't be ESD-clamped lower than 5V.
 
J

Joerg

Jan 1, 1970
0
Spehro said:
[This followup was posted to sci.electronics.design and a copy was sent
to the cited author.]
DC will never exceed 5V and abs max is 5.8V. So you think ESD or surges
(the usual machine-gun style bursts in EMC tests) are ok? We have it
clamped to a 5V rail but it could really lean into those clamp diodes.
This thread rattles around avoiding specifics. Is the "5V-tolerant"
input an input that has 3.3V as VDD?

Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the
I/O Rail VDD. These pins default to typical 8051 style with quasi-
bidirectional behavior with onboard pullup circuitry. The port pins can
also be programmed to be output driven by a totem pole output to the VDD
rail.

I'd (thankfully) almost forgotten about those miserable quasi
bi-directional port pins.

The schematic on page 161 does not appear to show the brief hard
(~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s
have. If it's present it would be back of the ESD circuitry anyway.

https://www.silabs.com/Support Documents/TechnicalDocs/C8051F02x.pdf

The problem is that, as usual, they write nothing about what's in the
Schmitt buffer at the bottom of that schematic. Sometimes I wish IC
designers were closer to the board level world and thus release more of
the info that we really need. Because we board level guys have to deal
with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like
in this case we have to get the whole thing through myriad agency certs
which require good rationale and math.
 
J

Joerg

Jan 1, 1970
0
Jim said:
Spehro said:
On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas

[This followup was posted to sci.electronics.design and a copy was sent
to the cited author.]

DC will never exceed 5V and abs max is 5.8V. So you think ESD or
surges
(the usual machine-gun style bursts in EMC tests) are ok? We have it
clamped to a 5V rail but it could really lean into those clamp diodes.
This thread rattles around avoiding specifics. Is the "5V-tolerant"
input an input that has 3.3V as VDD?

Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the
I/O Rail VDD. These pins default to typical 8051 style with quasi-
bidirectional behavior with onboard pullup circuitry. The port pins can
also be programmed to be output driven by a totem pole output to the VDD
rail.
I'd (thankfully) almost forgotten about those miserable quasi
bi-directional port pins.

The schematic on page 161 does not appear to show the brief hard
(~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s
have. If it's present it would be back of the ESD circuitry anyway.

https://www.silabs.com/Support Documents/TechnicalDocs/C8051F02x.pdf
The problem is that, as usual, they write nothing about what's in the
Schmitt buffer at the bottom of that schematic. Sometimes I wish IC
designers were closer to the board level world and thus release more of
the info that we really need. Because we board level guys have to deal
with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like
in this case we have to get the whole thing through myriad agency certs
which require good rationale and math.

It's management. Note how LTspice is going all encrypted?

You meant damagement? :)

And Analog Devices modeling efforts are now managed by a MARKETING VP,
and they are ultimately heading to requiring simulation of their parts
ONLY on their web-based simulator.

That would be a marketing decision that borders on stupid.
 
J

Joerg

Jan 1, 1970
0
Jim said:
Jim said:
Spehro Pefhany wrote:
On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas

[This followup was posted to sci.electronics.design and a copy was sent
to the cited author.]

DC will never exceed 5V and abs max is 5.8V. So you think ESD or
surges
(the usual machine-gun style bursts in EMC tests) are ok? We have it
clamped to a 5V rail but it could really lean into those clamp diodes.
This thread rattles around avoiding specifics. Is the "5V-tolerant"
input an input that has 3.3V as VDD?

Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the
I/O Rail VDD. These pins default to typical 8051 style with quasi-
bidirectional behavior with onboard pullup circuitry. The port pins can
also be programmed to be output driven by a totem pole output to the VDD
rail.
I'd (thankfully) almost forgotten about those miserable quasi
bi-directional port pins.

The schematic on page 161 does not appear to show the brief hard
(~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s
have. If it's present it would be back of the ESD circuitry anyway.

https://www.silabs.com/Support Documents/TechnicalDocs/C8051F02x.pdf

The problem is that, as usual, they write nothing about what's in the
Schmitt buffer at the bottom of that schematic. Sometimes I wish IC
designers were closer to the board level world and thus release more of
the info that we really need. Because we board level guys have to deal
with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like
in this case we have to get the whole thing through myriad agency certs
which require good rationale and math.
It's management. Note how LTspice is going all encrypted?
You meant damagement? :)

And Analog Devices modeling efforts are now managed by a MARKETING VP,
and they are ultimately heading to requiring simulation of their parts
ONLY on their web-based simulator.
That would be a marketing decision that borders on stupid.

I was there (San Jose) last August trying to convince them of the best
way to do modeling... let me see the real netlist and then I'd match
it behaviorally. The MARKETING VP nixed the idea.

(I even showed them various posts from this newsgroup complaining
about model quality... did no good.)

Then I assume they'll never understand why, when it comes to performance
and cost is not a major issue, I always default to LTC and never even
look at AD unless I can't find a chip at LTC. This is because LTC has
behavioral models that work in LTSpice and AD does not.

Same with TI. Who in their right mind would install and learn half a
dozen competing "free" simulators? If they can't understand that LTSpice
is the de facto winner, oh well.
 
J

Joerg

Jan 1, 1970
0
Fred, my news server did not carry your post. Maybe it came via
google groups?

whatsoever in a mixed signal low power digital environment. ...


It makes perfect sense to clamp. Stuff operated in a rough environment
has to have all inputs clamped or things will fry. Surges, bursts,
Lighting, and so on.

... The high
voltage tolerant inputs are a variation of the theme shown below in one
form or another. Operation is self-explanatory:
Your line breaks don't work. Had to do a "selective re-wrap" or it wuold
have garbled your ASCII schematic.


The PMOS keeper would make for a pretty leaky input, drawing quite some
current. Else it would become slow because the series NMOS loses steam
as the input voltage approaches VDD.

That looks vaguely like my USB patent on the work I did for Intel.
I'll dredge that up and post it.

It's I/O lines in my case, pretty much all uC offer I/O on all ports
except where comparators are piped out separately. So it may be more
like in Jim's post yesterday, the classic double-FET "semiconductor relay".

But all this doesn't really matter, since there isn't any data when the
oxide or whatever is the weakest link will pop if abs max says 5.8V. For
short spikes it will usually hold much higher but the datasheet is kind
of incomplete in that domain. That's what I'd like to know, how high for
spikes?
 
J

Joerg

Jan 1, 1970
0
Jim said:
Jim said:
Jim Thompson wrote:
Spehro Pefhany wrote:
On Tue, 25 Jun 2013 22:21:52 -0700, Michael Karas

[This followup was posted to sci.electronics.design and a copy was sent
to the cited author.]

DC will never exceed 5V and abs max is 5.8V. So you think ESD or
surges
(the usual machine-gun style bursts in EMC tests) are ok? We have it
clamped to a 5V rail but it could really lean into those clamp diodes.
This thread rattles around avoiding specifics. Is the "5V-tolerant"
input an input that has 3.3V as VDD?

Yes, the SiLabs C8051F020 type part nominally uses a 3.3V supply for the
I/O Rail VDD. These pins default to typical 8051 style with quasi-
bidirectional behavior with onboard pullup circuitry. The port pins can
also be programmed to be output driven by a totem pole output to the VDD
rail.
I'd (thankfully) almost forgotten about those miserable quasi
bi-directional port pins.

The schematic on page 161 does not appear to show the brief hard
(~100:1) pullup on 0->1 port-pin transition that old-skule 80C51s
have. If it's present it would be back of the ESD circuitry anyway.

https://www.silabs.com/Support Documents/TechnicalDocs/C8051F02x.pdf

The problem is that, as usual, they write nothing about what's in the
Schmitt buffer at the bottom of that schematic. Sometimes I wish IC
designers were closer to the board level world and thus release more of
the info that we really need. Because we board level guys have to deal
with ESD pulses, RF bursts, nearby lightning, and whatnot. And then like
in this case we have to get the whole thing through myriad agency certs
which require good rationale and math.
It's management. Note how LTspice is going all encrypted?

You meant damagement? :)


And Analog Devices modeling efforts are now managed by a MARKETING VP,
and they are ultimately heading to requiring simulation of their parts
ONLY on their web-based simulator.

That would be a marketing decision that borders on stupid.
I was there (San Jose) last August trying to convince them of the best
way to do modeling... let me see the real netlist and then I'd match
it behaviorally. The MARKETING VP nixed the idea.

(I even showed them various posts from this newsgroup complaining
about model quality... did no good.)
Then I assume they'll never understand why, when it comes to performance
and cost is not a major issue, I always default to LTC and never even
look at AD unless I can't find a chip at LTC. This is because LTC has
behavioral models that work in LTSpice and AD does not.

Same with TI. Who in their right mind would install and learn half a
dozen competing "free" simulators? If they can't understand that LTSpice
is the de facto winner, oh well.

PSpice will run ANY non-encrypted model, as will LTspice, HSpice, any
Cadence tool, and most amateur spin-offs.

If you run a complicated switcher non-behavioral (and I had to do that)
the sims take forever. For designing SMPS that clearly is not the most
efficient method.

Encrypting so a model will run only on the parent tool turns me off.


Me, too.

What do you do if you want to mix LT and ADI and TI parts on your
board? You're screwed.

On high end designs I never do that, and there is no need to. You can
usually get everything at LTC. Except for some hardcore RF stuff and
then that gets simulated separately.

If it has to be cheap then no special ICs are used anyhow most of the
time. For example, my first mass-produced device with a boost converter
revolves around a CD40106 as the "highest-tech" chip. There is no
dedicated PWM chip because that would have added at least 10c back in
the early 90's.

Joerg, sounds like LT is happy as a clam with you. You're a locked-in
customer. Enjoy >:-}

Well, yeah, at some point you have to pick one and run with that. I have
made my choice, and that choice is LTC.
 
J

Joerg

Jan 1, 1970
0
Jim said:
[...]

If you run a complicated switcher non-behavioral (and I had to do that)
the sims take forever. For designing SMPS that clearly is not the most
efficient method.



Me, too.


On high end designs I never do that, and there is no need to. You can
usually get everything at LTC. Except for some hardcore RF stuff and
then that gets simulated separately.

If it has to be cheap then no special ICs are used anyhow most of the
time. For example, my first mass-produced device with a boost converter
revolves around a CD40106 as the "highest-tech" chip. There is no
dedicated PWM chip because that would have added at least 10c back in
the early 90's.


Well, yeah, at some point you have to pick one and run with that. I have
made my choice, and that choice is LTC.

"Most" of their stuff is good. I've had a recent situation where an
encrypted model works just fine on LTspice, but not on a PCB.

Same here, the LT6700 had a glitch on the chip and I was the unfortunate
one who had to discover that the hard way.

The FAE was flummoxed, referred the problem to factory... 4 months
have passed, no solution.

In my case the LTC design engineers looked at it right away, found out
that it was indeed a bug, fessed up, apologized, rolled up the sleeves
and corrected things. That left a very positive impression with me.

Over the years I experienced numerous similar situations with other,
larger manufacturers. The classic solution was an attempt to cover it up.

I posted the problem on the LTspice list, but was basically told,
"LTspice, love it or leave it" :-(

All I've been able to find out is that LTspice encrypted models are
behavioral internally.

They are, mostly. That is the reason why you can simulate switchers so
blazingly fast. This does come with pitfalls and (minor) risks but it
sure beats non-behavioral sims that take hours.
 
J

Joerg

Jan 1, 1970
0
Jim said:
Jim Thompson wrote:
[...]

They are, mostly. That is the reason why you can simulate switchers so
blazingly fast. This does come with pitfalls and (minor) risks but it
sure beats non-behavioral sims that take hours.

I've been at this simulation stuff so long, I can recall simulations
taking DAYS!

Same here. I still have the cloth-covered binders from Microsim. Got
that in 1990, I think. Before that I used ECA224.

But today's simulators (and CPU's) are so much faster... it's rare for
a complex simulation, at device-level, to take more than 20-30
minutes.

Patience is a virtue ;-)

Yeah, in the winter it's ok. But in July/August times it has happened
that too much simulating brought the office temps from 85F to over 90F.
 
J

Joerg

Jan 1, 1970
0
Jim said:
Jim said:
Jim Thompson wrote: [...]


I posted the problem on the LTspice list, but was basically told,
"LTspice, love it or leave it" :-(

All I've been able to find out is that LTspice encrypted models are
behavioral internally.

They are, mostly. That is the reason why you can simulate switchers so
blazingly fast. This does come with pitfalls and (minor) risks but it
sure beats non-behavioral sims that take hours.
I've been at this simulation stuff so long, I can recall simulations
taking DAYS!
Same here. I still have the cloth-covered binders from Microsim. Got
that in 1990, I think. Before that I used ECA224.

But today's simulators (and CPU's) are so much faster... it's rare for
a complex simulation, at device-level, to take more than 20-30
minutes.

Patience is a virtue ;-)
Yeah, in the winter it's ok. But in July/August times it has happened
that too much simulating brought the office temps from 85F to over 90F.

You don't have A/C? Admittedly, my office runs about 5°F above the
rest of the house, but I can cure that by turning on a squirrel-cage
blower sitting in the office doorway ;-)

We do have A/C but don't run it. Our power prices have been
californicated. One of those stupid super-progressive inverse tier
systems where, if you work harder and use more electricity, you get
punished :-(

The evap cooler doesn't quite reach to this end of the house. Still
trying to figure how to mount a 2nd evap unit on the garade, ducting it
through there and into the hallway next to the office. That'll be one
very complicated duct, and since they don't sell fire-proof flexible
material of sufficient diameter I'd get to build all that myself.
 
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