As long as you are very confident about your loop and nobody re-spins
the board without a brief bypass capacitance review. Designing a loop
for an LDO feels like walking on egg shells, almost like PID tuning
where after numerous Ziegler-Nichols iterations it suddenly works but
nobody is 100% sure why.
If you make your own ldo from an opamp and a power fet, the loop
dynamics is easy... especially so if you can use an n-channel fet as a
follower.
unreg in
|
|
|
opamp |
ref--------- + d
out--------+------Rg--------g nmos fet
+----- - | s
| Ccomp |
| | |
| Rcomp |
| | |
+--------------------+------Rs---------+------- out
|
|
Cout
|
|
gnd
It's the damned LDO chips, with their pnp output stages and mysterious
compensations, that are dangerous.
Can't you design the flyback so it generates a very precise 3.3V and the
+/-12V remain outside the loop? Since you are a seasoned engineer your
opamp circuits mostly likely won't care whether it's 11V or 14V.
I need +12 min for headroom to make +-10.24 volt outputs, so we'll
design for maybe +13 nom, so we never dip below 12. That can put the
3.7 as high as 4.0, maybe even more transiently. These FPGA's are $90
each.
Feedback from the 3.3 would require the annoying optoisolated error
feedback thing, with its own problems. And still the possibility of
frying the logic if the loop ever gets unhappy for some reason. We're
getting our feedback from an aux winding referenced to the input side.
John