7805 failure mode

[Joerg]

Maybe for digital, but noise considerations for the analog supply
often dictate the use of a linear regulator or post regulator.

Sure, but it can be done. I had to do it many times. For example on
patient interfaces where weak signals had to be received but power had
to be brought out to that isolated head unit. Couldn't use DC ;-)

Actually, on one system they did use DC before I redesigned that area.
Two huge camera batteries, lead acid, 2lbs each, from the good old days.
Could really smash your foot if one fell out but then again you were
already in a hospital when that happened ....

 

[John Larkin]

I'd most likely do them all with home-cooked switchers. +12V is perfect
for a CD40106. It's got six inverters that can be used as PWM generators
and you need six voltages besides the +12V coming in



Why not a buck? At 100% duty cycle all there is between Vin and load is
the FET and the inductor which should cover the 3.3V Vin situation.

This latest gadget, or family of gadgets, get power from PoE
(ethernet) or a wall wart. We already have a custom flyback design
that accepts anything from 11 volts to 55, and delivers roughly +12,
-12, and +3.7. We use the 12's as-is for opamps and things, and will
use the homemade LDO to make 3.3 for most of the logic. The ldo takes
care of cross-regulation issues and maybe saves the logic from
toasting if the switcher hiccups. The drop is so low here that another
switcher would be overkill, I think.

John

 

[Joerg]

This latest gadget, or family of gadgets, get power from PoE
(ethernet) or a wall wart. We already have a custom flyback design
that accepts anything from 11 volts to 55, and delivers roughly +12,
-12, and +3.7. We use the 12's as-is for opamps and things, and will
use the homemade LDO to make 3.3 for most of the logic. The ldo takes
care of cross-regulation issues and maybe saves the logic from
toasting if the switcher hiccups. The drop is so low here that another
switcher would be overkill, I think.

As long as you are very confident about your loop and nobody re-spins
the board without a brief bypass capacitance review. Designing a loop
for an LDO feels like walking on egg shells, almost like PID tuning
where after numerous Ziegler-Nichols iterations it suddenly works but
nobody is 100% sure why.

Can't you design the flyback so it generates a very precise 3.3V and the
+/-12V remain outside the loop? Since you are a seasoned engineer your
opamp circuits mostly likely won't care whether it's 11V or 14V.

 

[John Larkin]

As long as you are very confident about your loop and nobody re-spins
the board without a brief bypass capacitance review. Designing a loop
for an LDO feels like walking on egg shells, almost like PID tuning
where after numerous Ziegler-Nichols iterations it suddenly works but
nobody is 100% sure why.

If you make your own ldo from an opamp and a power fet, the loop
dynamics is easy... especially so if you can use an n-channel fet as a
follower.

unreg in
|
|
|
opamp |
ref--------- + d
out--------+------Rg--------g nmos fet
+----- - | s
| Ccomp |
| | |
| Rcomp |
| | |
+--------------------+------Rs---------+------- out
|
|
Cout
|
|
gnd


It's the damned LDO chips, with their pnp output stages and mysterious
compensations, that are dangerous.

Can't you design the flyback so it generates a very precise 3.3V and the
+/-12V remain outside the loop? Since you are a seasoned engineer your
opamp circuits mostly likely won't care whether it's 11V or 14V.

I need +12 min for headroom to make +-10.24 volt outputs, so we'll
design for maybe +13 nom, so we never dip below 12. That can put the
3.7 as high as 4.0, maybe even more transiently. These FPGA's are $90
each.

Feedback from the 3.3 would require the annoying optoisolated error
feedback thing, with its own problems. And still the possibility of
frying the logic if the loop ever gets unhappy for some reason. We're
getting our feedback from an aux winding referenced to the input side.

John

 

[Joerg]

If you make your own ldo from an opamp and a power fet, the loop
dynamics is easy... especially so if you can use an n-channel fet as a
follower.

unreg in
|
|
|
opamp |
ref--------- + d
out--------+------Rg--------g nmos fet
+----- - | s
| Ccomp |
| | |
| Rcomp |
| | |
+--------------------+------Rs---------+------- out
|
|
Cout
|
|
gnd


It's the damned LDO chips, with their pnp output stages and mysterious
compensations, that are dangerous.

Ok, that ought to be stable. It slipped my mind that you have the luxury
of higher rails for the opamp so there is always headroom to drive the gate.

I need +12 min for headroom to make +-10.24 volt outputs, so we'll
design for maybe +13 nom, so we never dip below 12. That can put the
3.7 as high as 4.0, maybe even more transiently. These FPGA's are $90
each.

$90? Ouch!

Feedback from the 3.3 would require the annoying optoisolated error
feedback thing, with its own problems. And still the possibility of
frying the logic if the loop ever gets unhappy for some reason. We're
getting our feedback from an aux winding referenced to the input side.

Hmm, I never had problems with the opto thing. Except getting the
necessary cert paperwork for medical and in the beginning the purchasing
folks had a hard time to ensure a steady supply of the wide-body SMT
versions. Mostly because semi mfgs are sold and acquired all the time.

The aux winding method will be tolerance prone, there I understand your
need for post-regulation.

The slickest one was this: A carrier fed back via the switcher's
transformer. This was driven by the usual TLV431 deal on the secondary
side and the carrier regulated the switcher duty cycle.

 

[Damir]

If you make your own ldo from an opamp and a power fet, the loop
dynamics is easy... especially so if you can use an n-channel fet as a
follower.

unreg in
|
|
|
opamp |
ref--------- + d
out--------+------Rg--------g nmos fet
+----- - | s
| Ccomp |
| | |
| Rcomp |
| | |
+--------------------+------Rs---------+------- out
|
|
Cout
|
|
gnd


It's the damned LDO chips, with their pnp output stages and mysterious
compensations, that are dangerous.


I need +12 min for headroom to make +-10.24 volt outputs, so we'll
design for maybe +13 nom, so we never dip below 12. That can put the
3.7 as high as 4.0, maybe even more transiently. These FPGA's are $90
each.

Feedback from the 3.3 would require the annoying optoisolated error
feedback thing, with its own problems. And still the possibility of
frying the logic if the loop ever gets unhappy for some reason. We're
getting our feedback from an aux winding referenced to the input side.

John

 

[Fred Bloggs]

If you make your own ldo from an opamp and a power fet, the loop
dynamics is easy... especially so if you can use an n-channel fet as a
follower.

An LDO with an NFET follower? Maybe LDO means something else to you, but
generally makes no sense unless you boost the gate drive...

unreg in
|
|
|
opamp |
ref--------- + d
out--------+------Rg--------g nmos fet
+----- - | s
| Ccomp |
| | |
| Rcomp |
| | |
+--------------------+------Rs---------+------- out
|
|
Cout
|
|
gnd

Okay, you're getting there, but that is such an ugly drawing.

It's the damned LDO chips, with their pnp output stages and mysterious
compensations, that are dangerous.

LOL

 

[Joerg]

An LDO with an NFET follower? Maybe LDO means something else to you, but
generally makes no sense unless you boost the gate drive...

John has 12V on the opamps but only needs 3.3V out the source of the
FET. Plenty of gate drive, I'd say. Of course, whenever you and I happen
upon such a situation Murphy's law says there is not 12V rail.

Okay, you're getting there, but that is such an ugly drawing.

Looks like late-renaissance style.

 

[John Larkin]

An LDO with an NFET follower? Maybe LDO means something else to you, but
generally makes no sense unless you boost the gate drive...


Okay, you're getting there, but that is such an ugly drawing.

As has been mentioned elsewhere, a couple of times, the opamp is
powered by +12, so the fet can be driven to milliohms of Rds-on when
needed.

LOL

You never design electronics, so you laugh.

John

 

[John Larkin]

John has 12V on the opamps but only needs 3.3V out the source of the
FET. Plenty of gate drive, I'd say. Of course, whenever you and I happen
upon such a situation Murphy's law says there is not 12V rail.

The +12 and +3.8 are coming off a common flyback transformer. If
either fails, the product doesn't work, so they may as well fail
together.

Looks like late-renaissance style.

It's the idea that counts. Fred doesn't have ideas, only criticism of
ideas. Interesting, no?

John

 

[Joerg]

The +12 and +3.8 are coming off a common flyback transformer. If
either fails, the product doesn't work, so they may as well fail
together.

Yes, but that's quite an unusual case and it's under your control. Most
of the time I do not have anything but the one voltage that needs to be
regulated down. Of course, one could still use an inverter to create a
higher voltage just for the driver.

I'd still use an opto feedback to generate a stable 3.3V out of the
flyback ;-)

[...]