75HC573 again...

[DaveC]

Hello, Id appreciate comments on the Schematic found here...

http://homepages.paradise.net.nz/ohiro/latch.gif

It's part of a bus I'm designing for a PIC. I wanted to speed things up a
little so I made the WRITE latch capture the value of the last READ
operation. I hope I've done this ok.

Any way I'm still a little up in the air over the AC characteristics of the
75HC573 and need a little clarification.

The part of concern is when PIC READ goes low the Output Control of U2 may
get disabled before U1 is able to latch the data on the 8 bit PIC data I/O
bus. I think the inverter U4A should help? .. Here is how I worked it out.

a) 8ns for U4A + 13ns for U2 OC = 21ns
..vs.
b) 2ns for D1 + 10ns for U1 LE = 12ns

So long as b) is less then a) I should be ok.. or should I replace U4A with
three inverters to be safe.


Thanks,
DaveC

 

[Frank Bemelman]

Hello, Id appreciate comments on the Schematic found here...

http://homepages.paradise.net.nz/ohiro/latch.gif

It's part of a bus I'm designing for a PIC. I wanted to speed things up a
little so I made the WRITE latch capture the value of the last READ
operation. I hope I've done this ok.

Any way I'm still a little up in the air over the AC characteristics of the
75HC573 and need a little clarification.

The part of concern is when PIC READ goes low the Output Control of U2 may
get disabled before U1 is able to latch the data on the 8 bit PIC data I/O
bus. I think the inverter U4A should help? .. Here is how I worked it out.

a) 8ns for U4A + 13ns for U2 OC = 21ns
.vs.
b) 2ns for D1 + 10ns for U1 LE = 12ns

So long as b) is less then a) I should be ok.. or should I replace U4A with
three inverters to be safe.

I don't understand what you want. Is this a PIC with a parallel port,
such as the 16F877 ? Or are you generating the RD/WR/WE/OE all by
yourself in software? Where is this 2nd databus going to? If it is a
bidirectional bus, how will you know when it's safe to place something
on it, or when to read from it?

 

[DaveC]

Yup, Sorry about that.. Here is an update.

http://homepages.paradise.net.nz/ohiro/latch2.gif

I've completed most of the connections here and added the other half of
the data I/O. I'm building my own bus to interface with SRAM, ISA Cards
and so on. So No I'm not using the 16F877 in parallel slave mode. The PIC
is more of a master here.

The Write and Read High / Low inputs are active High and addresed with a
BDC to Decimal decoder (CD4028BC). So I have three extra address lines
from the PIC for this. Still much not here like another 4 latches for
address and so on.


Any way the origional question was really just about the timming of a
High / Low transition on (now called) the Read lines . and if OC on U2
would disable U2's outputs before LE on U1 had a chance to latch the
data.


Thanks,

DaveC

 

[Frank Bemelman]

Yup, Sorry about that.. Here is an update.

http://homepages.paradise.net.nz/ohiro/latch2.gif

I've completed most of the connections here and added the other half of
the data I/O. I'm building my own bus to interface with SRAM, ISA Cards
and so on. So No I'm not using the 16F877 in parallel slave mode. The PIC
is more of a master here.

The Write and Read High / Low inputs are active High and addresed with a
BDC to Decimal decoder (CD4028BC). So I have three extra address lines
from the PIC for this. Still much not here like another 4 latches for
address and so on.


Any way the origional question was really just about the timming of a
High / Low transition on (now called) the Read lines . and if OC on U2
would disable U2's outputs before LE on U1 had a chance to latch the
data.


Thanks,

DaveC

I still don't get it. If you plan to write/latch something into U1, you
will have to program the relevant PIC I/O to outputs, using the direction
register. Before you can do that, you have to disable U2's outputs. So,
first READ goes low, then you set the PIC to transfer data to U1. I guess.

Where is that CD4028BC you are talking about? Where are the /WR /RD /OE
/CE lines of that external ram you want to control? Is it a 16 bit bus?

Or do you want to have a universal 16 bit i/o where every pin can be
input or output? If so, I'd recommend pullup resistors on the
outputs/inputs,
so they won't float if U1 and U3 are disabled.

 

[Frank Bemelman]

"DaveC" <[email protected]> schreef in bericht

[snip]

I did also say that the Schematic is not complete, because the rest of it
has nothing to do with what my question was. The SRAM control lines are
set with the other 4 latchs I was talking about. Just keep thinking..
Read High - Low transition.

Seems all right then. Personally I prefer gates and not diodes, but
you chose the resistors pretty low, 1K.