74hc165 sh/pl problem

[Bill Sloman]

Hi, i'm hpoing someone can shed som light on the anomalous behavior i am
experiencing with thes shift regs...

I have a microsecond timing cicuit where two hc4040 ripple counters are
read by 3 165 shift registers. After the 4040's have been clocked and
settled i initiate a paralell load on the 165's. Somehow the data which
is clocked out of the 165's randomly differs to the data values
avaliable on the parallel input pins... Any Ideas?????

As Win Hill has pointed out, the 74HC4040 is a 12-stage ripple
counter, and two of them can take quite a long time to settle after a
clock edge.

According to page 5 of the Philips data sheet

http://www-eu2.semiconductors.com/acrobat/datasheets/74HC_HCT4040_CNV_2.pdf

the propagation delay from the clock input to the Q0 output at 4.5V
can be as high as 45nsec, and from Q0 to Q1 etc 30nsec. Over two
counters this adds up to 750nsec, which is quite a while for a counter
that can toggle at 20MHz.

Are you waiting long enough after the 4040's have been clocked before
you load their outputs into your shift register?