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74164 Totem-Pole Outputs in Parallel

Discussion in 'Beginner Electronics' started by Computer Nerd Kev, Aug 16, 2013.

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  1. Hello,

    I am working on a circuit in which I want to use 74164 SIPO
    Shift Registers as something like basic DACs (Shift Registers
    outputting a stepped current).

    Whatever you want to call it, it involves connecting the
    outputs of the 74164s together through individual high value
    resistors so that current increases with each output going
    high, the parallel output driving the base of a transistor. I
    couldn't see a problem with the idea until I read this line in
    "Newnes Digital Logic IC Pocket Book" (P. 44):

    "Note that normal totem-pole outputs should not (except in a
    few special cases) be connected in parallel."

    Nothing is said regarding what these "special cases" might be,
    although if viewed from the perspecive of logic interfacing, I
    can see how mine may be one of them. Indeed it seems likely
    that the statement refers to cases such as in a wired-OR
    circuit where outputs are connected directly, without series

    Nevertheless, I saw need for clarification so I searched books
    and the internet for reference to TTL totem-pole outputs in
    parallel, but found nothing to directly address my concern.
    Hence I ask here for clarification on the matter.
  2. Ever had a look at the schematic of a totempole? Then you'd know that
    putting them in parallel will give a short from Vcc to Gnd when one is high
    and the other low. There is off course a collector resistor but way too low
    to stand the short circuit current for longer then some ns. Connecting
    resistors to the output will lower the current but you'll have to calculate
    carefully to stay within de margins of the chips fanout. Be aware that
    resistors tend to conduct current in both directions.

    petrus bitbyter
  3. Yep, the load on the output buffer transistor will be 1mA
    max., so the current required to drive it can be kept well
    within spec.. The resistors used can therefore be of high
    enough values to keep the currents between outputs very low.
    This is what I meant by my situation perhaps fitting with the
    "special cases" statement in the book.

    I was mainly wondering if there was anything wrong with adding
    current from multiple high outputs in this manner. I
    understand the totem-pole circuit, but I wondered if something
    in the IC circuit as a whole might be problematic in this

    Perhaps I'm too cautious and I should just build the thing and
    find out (which is probably what I'll do). On the other hand I
    though it was worth a question in case I was missing something
    already known.
  4. Expect you'll find it not to work out the way you want to. The old standard
    TTL can source less then 0.5mA though sink about 8mA. Newer LS do not do
    better. CMOS differs a lot but is not the same for all types. At least for
    TTL you have to realise that the output resistance for a high output is way
    much higher then for a low. You can work around a bit by using pull up
    resistors but it'll take quite some time to calculate the various resistors
    and even more time for experimentally fine tuning.

    petrus bitbyter
  5. Thanks for the warning, but at the very least the transistor
    will amplify the current, so I'll be able to keep well below
    those TTL current limits.

    I actually am using standard 74164s not LS or any other
    derivative as that's what I have to hand.
  6. Robert Baer

    Robert Baer Guest

    Your approach is a bit skewed.
    #1: You do not need high value resistors or the summing of their
    currents into a transistor.
    A better approach is to have each resistor go to a "summing junction"
    AKA inverting input of an operational amplifier; each current is thereby
    isolated and can be independently tweaked as needed.
    #2: The business of TTL totem-pole outputs in parallel relates to
    direct connection, and is discouraged even if inputs of simple inverters
    are driven in parallel, the problem is as follows if their outputs are
    connected in parallel:
    Each inverter has a slightly different delay, rise and fall - meaning
    some pullups are turning on(off) while others are still off(on).
    That creates a larger current spike in the supply line that WILL
    propagate to all other gates (and WILL skew timing because of spike
    ground currents).
    I say "larger" in that only ONE gate turning on(off) will create a
    spike as the pull-down transistor cannot turn off completely before the
    pull-up turns on due to base stored charge.
    #3: Using TTL for a digital drive for DAC purposes ain't elegant nor
    accurate as the logical "high" is not a fixed nor repeatable value; use
    CMOS instead with a precision supply.
  7. No doubt an Op-Amp with feedback will be more stable than my
    single transistor so I'll probably use one anyway, however I'm
    not sure how you can say a summing junction is isolated. All the
    shift register's outputs are still connected directly through
    the parallel resistors; couldn't I have tweaked the individual
    output resistances going into a single transistor amplifier?

    Thanks for explaining the problems with direct connection. The
    maximum speed I will have this circuit running at will be 1Hz,
    so even if that did apply to my case it sounds like it wouldn't
    be a problem.
    I knew it wasn't fixed, though in the same circuit conditions
    why wouldn't it be repeatable? In any case I'll try what I've
    got and if it doesn't work, then it won't be too hard to
    substitute in CMOS chips.

    Thanks for your help.
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