6502 and writing to latch

I've thought I had this particular matter planned out properly about
two different times now, but when I look at 6502 timings in relation to
my planned circuit already, I thought I'd ask to confirm.

Basically, I want to write to a latch (or well, a '374 octal
flip-flop), which has a positive-triggered clock. I should point out
that my decoding logic begins with a '139, using both O2 and A15 to
determine whether we're trying to access the upper or lower 32k, and
then I drill down from there. This means my latch /CE equivalent will
only be active for as long as O2 is. O2 seems to go low around mid-way
that the data lines are active, so this seems to be the best way to
handle any chip enables. But, of course, I only watch the latch to
grab data when the write signal is active as well, because later I'll
possibly add in a tri-state buffer to be able to read its contents back
out.

Anyhoo, so I figure if I invert both its /CE and the R/W signal, run
them through an AND gate, then invert the output of the AND gate going
into the clock of the latch (positive-triggered, remember), I *should*
be able to clock the latch at the proper time to grab the data lines,
since O2 goes low while the data lines are still active (and if O2 goes
low, my /CE is disabled, and the latch clock input goes high, which
should grab the current state of the data lines).

This is probably hard to digest with just my explanation of the
process, but if it doesn't make a lot of sense, perhaps someone with a
better knowledge of 6502 timings can simply share the "proper" way to
clock a positive-triggered latch in order to write to it. Though if my
blabbing does make sense, I'd be even happier to know if it should work
properly. lol. But any help to verify my solution or give a better
method would be much appreciated!

 

O2 (Phase 2) is the inverse of the main internal clock in a 6502, as I
recall from a long time ago. If you are concerned about latching the
data, then decode a *write cycle* ->

(Address of interest) & R/W = 0

If you want to get valid data, use phase 2 (it's there specifically for
that purpose), so you decode your CS from A[15:0] or some subset
thereof. Let this decoder run all the time if you're not worried about
power (and as the 6502 never was a fast device, there's not going to be
much).
Now when phase 2 goes low *when R/W is already low* and your CS is
valid, write the data.

That equates to a 3 input NOR attached to the CLK input of the latch.
To make it easy, you could run the CE (active low) and R/W through a 2
input OR, and put this output and the phase 2 signal to the inputs of a
2 input NOR. Don't underestimate the power of logic reduction

Given the slow bus cycle of a 6502 (if it's running at a blistering
2MHz then a bus cycle will be 500nS), you'll have 250nS from the time
phase 2 appears to get through the propagation delay of the final NOR
which should leave plenty (there's an understatement) of margin for
hold time on the latch. Setup time is already dealt with as the data
are valid long before phase 2 hits.

This is from memory, and I don't really feel like looking for a 6502
datasheet right now

A read is simplicity itself; decode your address as above (so it's the
same circuit anyway) , and gate the OE control on phase 2 = low & R/W
= high. The propagation delay of the gating will probably be sufficient
to get the necessary hold time for the input latches on the processor.


Cheers

PeteS