500MHz CPLDs

[Ted Lechman]

I need a small 500MHz downcounter that I would like to implement in a
CPLD-like device. Do you know of any out there? I would prefer not to
use an FPGA in this application - but trather a small count macrocell
device.

Thanks for the information
Ted - Utica, NY

 

[Rene Tschaggelar]

I need a small 500MHz downcounter that I would like to implement in a
CPLD-like device. Do you know of any out there? I would prefer not to
use an FPGA in this application - but trather a small count macrocell
device.

They are not out yet. Not this fast.
Give them another year.

Rene

 

[Dana Raymond]

To get around this limitation use a slower CPLD with one or two bits of
external FFs for counting. PECL FFs and possibly counters exist, though
interfacing to them takes a little more work.

Dana Frank Raymond

 

[Bill Sloman]

I need a small 500MHz downcounter that I would like to implement in a
CPLD-like device. Do you know of any out there? I would prefer not to
use an FPGA in this application - but rather a small count macrocell
device.

You might want to post this question on comp.arch.fpga, where the real
CPLD freaks hang out.

Peter Alfke, an applications engineer from Xilinx, hangs out there.
IIRR he did a 500MHz counter in a Xilinx chip a couple of generations
ago, though it took a lot of tricky design to make it work. It might
be sensible to lurk a bit to make sure you aren't going to post a
frequently asked question.

A Google Groups search on the news group threw up a more recent thread
"Re: Counter Metrics" from July 2002, where Peter Alfke claims that up
to 1GHz is now possible for some types of counter.

It could be worth e-mailing him directly ...

 

[Ted Lechman]

Thanks for your suggestions - Xilinx (Virtex) and Altera (STratix) are
too slow (I'm guessing because BiCMOS only goes up to at most 400MHz,
cold). So therefore, like you've suggested, I've decided to use
something like an ONSemi MC100EP016AFA ECL 8-bit presetable upcounter
- good above 1GHz at 85 deg C. So I've refined my search to low
density (high current) ECL PLA's, assuming such exist.
Thanks
ted lechman

 

[Bill Sloman]

Thanks for your suggestions - Xilinx (Virtex) and Altera (STratix) are
too slow (I'm guessing because BiCMOS only goes up to at most 400MHz,
cold). So therefore, like you've suggested, I've decided to use
something like an ONSemi MC100EP016AFA ECL 8-bit presetable upcounter
- good above 1GHz at 85 deg C. So I've refined my search to low
density (high current) ECL PLA's, assuming such exist.
Thanks
ted lechman

It wasn't me who suggested the ECL parts, though I have used ECLinPS
and I know that it is fast enough to do your job.

Lattice have some 455MHz parts

http://www.latticesemi.com/products/cpld/index.cfm

There used to be some ECL CPLD's around, but they offered very few
gates, and have long since vanished.

IIRR there was a firm in California who had some relatively fast MOS
FPGA's, but they haven't lasted either. That was disappointing.

CMOS can go faster than 400MHz

http://asic.postech.ac.kr/2.Research/2.Publications/ijournal/27.pdf

and I'm a bit surprised that no-one is selling programmable parts for
this speed.

 

[Dana Raymond]

I don't know if it matters, but I was the one who suggested using PECL
devices for the LSB and possibly NLSB of the counter. The rest can be
implemented in CPLD/FPGA/Whatever.

Dana Frank Raymond

 

[Fred Bloggs]

I don't know if it matters, but I was the one who suggested using PECL
devices for the LSB and possibly NLSB of the counter. The rest can be
implemented in CPLD/FPGA/Whatever.

Oookay- then you are now entitled to place an asterisk (symbolizes gold
star for outstanding contributions) next to your NG name for the
remainder of September.

 

[Bill Sloman]

Oookay- then you are now entitled to place an asterisk (symbolizes gold
star for outstanding contributions) next to your NG name for the
remainder of September.

Read the thread, Fred, and stop posting quotations out of context. It
is called text-chopping, and earns you a session on Jim Thompson's
favourite ant-hill.

 

[Fred Bloggs]

Read the thread, Fred, and stop posting quotations out of context. It
is called text-chopping, and earns you a session on Jim Thompson's
favourite ant-hill.

I don't really see where you need a whole lot of context to understand
the text quoted. And do you have any idea at all of how many kinds of
"counters" there are?- escapes me how you can attempt to answer the
pathetically vague OP.

 

[Keith R. Williams]

Thanks for your suggestions - Xilinx (Virtex) and Altera (STratix) are
too slow (I'm guessing because BiCMOS only goes up to at most 400MHz,
cold). So therefore, like you've suggested, I've decided to use
something like an ONSemi MC100EP016AFA ECL 8-bit presetable upcounter
- good above 1GHz at 85 deg C. So I've refined my search to low
density (high current) ECL PLA's, assuming such exist.

Peter Alfke (of Xilinx) likes to see how fast he can push their latest
and greatest. IIRC, he has done a counter at >1GHz in a VirtexII. He
uses a Johnson counter for the prescaler to the the FPGA standard
"ripple" counter. Note that he knows how to squeeze the technology, so
I'm not certain how easy this is to do for the "outsider". As Bill
suggested, you might want to try asking on comp.arch.fpga.

The VirtexE and later have LVPECL as an input option. If your
prescaler allows 3.3V operation, this might be an option.

 

[Bill Sloman]

I don't really see where you need a whole lot of context to understand
the text quoted. And do you have any idea at all of how many kinds of
"counters" there are?- escapes me how you can attempt to answer the
pathetically vague OP.

You seem to have suffered a catastrophic decline in your capacity to
see things.

Dana Raymond was reacting to my denial of having proposed the use of
an ECL prescaler, by taking responsibility for the suggestion, rather
than ostentatiously claiming the credit for it - which is what your
put-down implies.

Peter Alfke's postings on realising fast counters in Xilinx chips are
quite explicit on the speed differences between various sorts of
counters - having pointed the OP at a good source for this
information, I saw no necessity to make this point myself. I do know
the difference between Johnson, ripple and synchronous counters, but
my expertise isn't in Peter Alfke's class. Is yours?

 

[Fred Bloggs]

You seem to have suffered a catastrophic decline in your capacity to
see things.

Dana Raymond was reacting to my denial of having proposed the use of
an ECL prescaler, by taking responsibility for the suggestion, rather
than ostentatiously claiming the credit for it - which is what your
put-down implies.

The OP "announced" that the ECL ( or maybe EKL to you) '016 would do the
job, you responded with some gibberish, and Raymonds chimes in with
reminder that his post was first to mention ECL- actually he suggested
"PECL" and mentioned that "possibly counters exist" in the logic family
or whatever.

Peter Alfke's postings on realising fast counters in Xilinx chips are
quite explicit on the speed differences between various sorts of
counters - having pointed the OP at a good source for this
information, I saw no necessity to make this point myself. I do know
the difference between Johnson, ripple and synchronous counters, but
my expertise isn't in Peter Alfke's class. Is yours?

I don't know much about him other than the one app note on the 400MHz
counter- I don't recall anything about a comparative study of counter
types. In general, I don't think it's a good idea to run a particular
technology right up to the max frequency- where all you can do is toggle
a FF- so this flagged his paper as more of a marketing effort than a
contribution to the art.

 

[Bill Sloman]

The OP "announced" that the ECL ( or maybe EKL to you) '016 would do the
job, you responded with some gibberish, and Raymonds chimes in with
reminder that his post was first to mention ECL- actually he suggested
"PECL" and mentioned that "possibly counters exist" in the logic family
or whatever.

Sue whoever sold you that speed-reading course - it seems to have
wrecked your comprehension. PECL is just Motorola's name for ECL run
between +5V and 0V, rather than 0V and -4.5V as God intended. Saves
you a power supply, but makes the grounding clip on your scope probe
into a deadly weapon.

I don't know much about him other than the one app note on the 400MHz
counter- I don't recall anything about a comparative study of counter
types. In general, I don't think it's a good idea to run a particular
technology right up to the max frequency - where all you can do is toggle
a FF - so this flagged his paper as more of a marketing effort than a
contribution to the art.

You'd have to lurk on comp.arch.fpga to get some insight into Peter
Alfke.
He works for Xilinx as an application engineer, and to that extent,
everything he does is a marketing effort, but he is a top flight
applications engineer - perhaps comparable with Jim Williams of Linear
Technology, but rather more accessible.

 

[Fred Bloggs]

Sue whoever sold you that speed-reading course - it seems to have
wrecked your comprehension. PECL is just Motorola's name for ECL run
between +5V and 0V, rather than 0V and -4.5V as God intended. Saves
you a power supply, but makes the grounding clip on your scope probe
into a deadly weapon.

LOL- I notice ONSemi now uses PECL, NECL, and LVECL- but you're still a
NUCL-head as ever. Wonder what they call the old +2,-3.2V setup to
DC-couple directly into 50 ohms to GND? PNECL?

You'd have to lurk on comp.arch.fpga to get some insight into Peter
Alfke.
He works for Xilinx as an application engineer, and to that extent,
everything he does is a marketing effort, but he is a top flight
applications engineer - perhaps comparable with Jim Williams of Linear
Technology, but rather more accessible.

One word of advice is that you draw a very thick line around the FPGA
whenever you seek information from these people as they are rather
clueless outside the boundary. I was just dealing with a company out of
two offices and receiving ridiculously contradictory information to the
point of the various reps going at eachother. The only way to deal with
them was to design them and their proprietary systems out of the
equation- they are out about $250K in the near term- but also enabled me
to totally nix another bunch of hucksters and their $1M custom A/D
development too- so I do thank them for that.

 

[Winfield Hill]

Fred Bloggs wrote...

One word of advice is that you draw a very thick line around the FPGA
whenever you seek information from these people as they are rather
clueless outside the boundary. I was just dealing with a company out of
two offices and receiving ridiculously contradictory information to the
point of the various reps going at eachother. The only way to deal with
them was to design them and their proprietary systems out of the
equation- they are out about $250K in the near term- but also enabled me
to totally nix another bunch of hucksters and their $1M custom A/D
development too- so I do thank them for that.

Now we're getting somewhere. That's a story, or set of stories
that you should expound upon for all of us stuck here in the
hinterlands. Details, we want details!

Thanks,
- Win

 

[Bill Sloman]

LOL- I notice ONSemi now uses PECL, NECL, and LVECL- but you're still a
NUCL-head as ever. Wonder what they call the old +2,-3.2V setup to
DC-couple directly into 50 ohms to GND? PNECL?

"Test gear". You need yet another power supply, and - as with PECL -
it is a bit too easy to blown up the output transistors by briefly
grounding a signal line, but it allows you to use the 50R to ground
termination built into fast oscilloscope inputs. Motorola used to
prescribe it for all their performace tests.

I'd guess that NECL was Negative- or Normal-ECL, and LVECL would be
low voltage, which has the same advantages for ECL as it does for any
other sort of logic

One word of advice is that you draw a very thick line around the FPGA
whenever you seek information from these people as they are rather
clueless outside the boundary. I was just dealing with a company out of
two offices and receiving ridiculously contradictory information to the
point of the various reps going at eachother. The only way to deal with
them was to design them and their proprietary systems out of the
equation- they are out about $250K in the near term- but also enabled me
to totally nix another bunch of hucksters and their $1M custom A/D
development too- so I do thank them for that.

Sturgeon's Law say that 90% of everything is rubbish, and reps tend to
illustrate that rule. You do come across application engineers who
talk sense - Analog Devices have a few, Linear Technology have got Jim
Williams, National Semiconductor had Bob Widlar (who wrote a mean
application note) and have Bob Pease - and Peter Alfke does seem to
belong to that useful little group.

Distrusting reps is a good rule of thumb, but there are exceptions.
I'd be very surprised to run into a useful rep from Texas Instruments.
bit I guess that even that is possible.

 

[Fred Bloggs]

I'd guess that NECL was Negative- or Normal-ECL, and LVECL would be
low voltage, which has the same advantages for ECL as it does for any
other sort of logic

You will find that the LVECL is specified to run significantly faster
because of the smaller voltage swings.