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5-bit synchronous sequence recognizer design

Discussion in 'Electronics Homework Help' started by EngineeringFailure, Nov 3, 2016.

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  1. EngineeringFailure


    Nov 3, 2016
    I am trying to design a 5-bit sequence recognizer. The circuit has to detect two sequences of bits. The first sequence is 11001. The second is 10010. The output when no sequence is detected should be 00. When the 1st input sequence is detected, the output should be 01. When the second sequence is detected, the output should be 10. Overlapping should also be detected. I'm designing a mealy type machine

    The specifications of the assignment say that it has to be one finite state machine to detect both the sequences(i.e one circuit block).

    The first step that we always do is draw a state diagram or state table whichever is easier. I chose to draw the state diagram first.

    Here is my state diagram:

    this one.jpg

    Is my state diagram correct?
    Last edited: Nov 3, 2016
  2. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    Jan 21, 2010
    Your image is not visible.

    Upload it here, don't point at an image at another forum that presumably requires that you are logged in to view it.
  3. EngineeringFailure


    Nov 3, 2016
    Just uploaded it. Can you see it?
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