Connect with us

4017 chip won't behave!

Discussion in 'Electronic Design' started by [email protected], Dec 9, 2012.

Scroll to continue with content
  1. Guest

    HI all,

    I've been having problems with a timer circuit I'm building. It uses a chain of seven CD4017BE decade counters. The first in the chain gets clock pulses from a 555 running at about 10Hz. I take the last output from this chip (puts out one pulse for every 10 input pulses) and feed it to the input of the next chip where the same thing is done and so on so the pulses get time-divided by 10 at each stage. All's fine up to decade 4, then something oddhappens. Instead of just pulsing, the output goes high and remains high until the next pulse comes along and toggles it back to low, so this stage's output is high for far too long.
    For this prototype I'm using rat's nest on PCB construction and believe I've paid proper attention to grounding and decoupling. Funny thing is, if I transfer the components over to proto-board, the problem disappears. Do these symptoms ring a bell with anyone? Is the 4017 particularly layout-sensitive?
    It's driving me nuts.

    Any ideas?
     
  2. It uses a chain of seven CD4017BE decade counters. The first in the
    chain gets clock pulses from a 555 running at about 10Hz. I take the
    last output from this chip (puts out one pulse for every 10 input
    pulses) and feed it to the input of the next chip where the same thing
    is done and so on so the pulses get time-divided by 10 at each stage.
    All's fine up to decade 4, then something odd happens. Instead of just
    pulsing, the output goes high and remains high until the next pulse
    comes along and toggles it back to low, so this stage's output is high
    for far too long.
    believe I've paid proper attention to grounding and decoupling. Funny
    thing is, if I transfer the components over to proto-board, the problem
    disappears. Do these symptoms ring a bell with anyone? Is the 4017
    particularly layout-sensitive?
    Missing power or ground connection?

    Most chips in the CD series will still work without at least one of
    these connections by powering or grounding themselves from the
    input-catching diodes as long as at least one input is in a suitable
    state. When all inputs go to '0' (if the + is missing) or to '1' (if
    the Ov is missing) the chip will get in a tangle. The chip will also be
    isolated from its power supply decoupling, so it will be susciptible to
    spurious effects from sharp edges on input waveforms or even nearby
    tracks.

    A floating reset line can also cause havoc.
     
  3. Tim Williams

    Tim Williams Guest

    Could be signal bounce in your "rat's nest"?

    More likely with 74LS and anything else with enough speed and drive (74HC,
    AC, etc.), and rather unlikely with the weak outputs from CD4k, but...

    This is different from supply decoupling: a sufficiently long wire or
    trace will bounce (potentially causing multiple transitions) or rise
    slowly (confusing clock inputs). The result can be seen on the 'scope.

    If nothing else, you can try RC-filtering the signals and adding a schmitt
    trigger buffer to maintain the necessary edge speed for the clock input.

    Tim

    --
    Deep Friar: a very philosophical monk.
    Website: http://seventransistorlabs.com

    HI all,

    I've been having problems with a timer circuit I'm building. It uses a
    chain of seven CD4017BE decade counters. The first in the chain gets clock
    pulses from a 555 running at about 10Hz. I take the last output from this
    chip (puts out one pulse for every 10 input pulses) and feed it to the
    input of the next chip where the same thing is done and so on so the
    pulses get time-divided by 10 at each stage. All's fine up to decade 4,
    then something odd happens. Instead of just pulsing, the output goes high
    and remains high until the next pulse comes along and toggles it back to
    low, so this stage's output is high for far too long.
    For this prototype I'm using rat's nest on PCB construction and believe
    I've paid proper attention to grounding and decoupling. Funny thing is, if
    I transfer the components over to proto-board, the problem disappears. Do
    these symptoms ring a bell with anyone? Is the 4017 particularly
    layout-sensitive?
    It's driving me nuts.

    Any ideas?
     
  4. Guest

    The 4017 already has Schmidt trigger input anyway. I did consider long traces, but they're not long. Plus when I hook the thing up using proto-board I'm using patch wires that are several inches long and they don't seem to cause any problem; the thing seems to prefer protoboard and long patch wires to my PCB arrangement!
     
  5. Guest

    The main idea is to read the datasheet with comprehension. Phrases like "each decoded output remains high for one full clock cycle" and " a carry out signal completes one full cycle every 10 input clock cycles" should be clues. The datasheet is telling you the first O9 output stays high for 0.1 sec,the period of the 555 clock, and has a period of 10x0.1=1 sec. So the second counter O9 will remain high for 1s and has a period of 10 sec. The third counter O9 remains high for 10s and has a period of 100 sec, and the fourth counter O9 remains high for 100s and has a period of 1000 sec.In your case, the simplest fix to get the final output pulse width you want is to use another 555 like so:
    Please view in a fixed-width font such as Courier.

    ..
    ..
    ..
    ..
    .. V+
    .. |
    .. .---[R]------+ 0.7xRC
    .. | | 555
    .. | -------------- ->| |<-
    .. | | V+ | __
    .. +-----+THRESH OUT|--> | |
    .. | | | __| |__
    .. O9 +-----+TRIG DIS|-.
    .. _. ..._ | | | |
    .. | | >--|-----|RST GND | |
    .. __| |__ | --------------- |
    .. | | |
    .. +-------------|--------'
    .. C | |
    .. === |
    .. | |
    .. '-------------+
    .. |
    .. ---
    .. ///
    ..
    ..
    ..
     
  6. Guest

    Revise the 555 one-shot to be as shown:

    Please view in a fixed-width font such as Courier.

    ..
    ..
    ..
    ..
    .. V+
    .. |
    .. .-[R]------+ 1.1xRC
    .. | | 555
    .. | -------------- ->| |<-
    .. | | V+ | __
    .. +---+THRESH OUT|--> | |
    .. | | | __| |__
    .. O9 .--[10K]-+----|---+TRIG DIS|-.
    .. _. ..._ | | | | | |
    .. | | >-+-------------|---|RST GND | |
    .. __| |__ | | --------------- |
    .. | | | |
    .. | +-----------|--------'
    .. 470p| C | |
    .. === === |
    .. | | |
    .. '----+-----------+
    .. |
    .. ---
    .. ///
    ..
    ..
    ..
     
  7. <> schreef in bericht
    HI all,

    I've been having problems with a timer circuit I'm building. It uses a chain
    of seven CD4017BE decade counters. The first in the chain gets clock pulses
    from a 555 running at about 10Hz. I take the last output from this chip
    (puts out one pulse for every 10 input pulses) and feed it to the input of
    the next chip where the same thing is done and so on so the pulses get
    time-divided by 10 at each stage. All's fine up to decade 4, then something
    odd happens. Instead of just pulsing, the output goes high and remains high
    until the next pulse comes along and toggles it back to low, so this stage's
    output is high for far too long.
    For this prototype I'm using rat's nest on PCB construction and believe I've
    paid proper attention to grounding and decoupling. Funny thing is, if I
    transfer the components over to proto-board, the problem disappears. Do
    these symptoms ring a bell with anyone? Is the 4017 particularly
    layout-sensitive?
    It's driving me nuts.

    Any ideas?


    Reading the thread so far there must be something wrong on your PCB. A
    short, an open, a wrong or missing connection, a bad solder joint or
    something like that. I simply can't come to another conclusion. Finding it
    may take some old-fashioned, tedious legwork. Use your eyes, maybe a
    magnifier and an ohmmeter that can measure real low resistances. Power- and
    ground connections are primary suspects, as stated already but there are no
    non-suspects. Did you try to increase the clock and check the circuit's
    behavior with a 'scope? As the breadboard version works, one does not expect
    flaws in the schematic. Nevertheless, if you can show it somehow I'd like to
    look at it.



    petrus bitbyter
     
  8. Guest

    Perhaps I can load something up to abse if it's still possible. Thanks for your comments and I fully agree with what you say, but Fred Bloggs has justraised other valid points which need to be looked at (thanks, Fred) but there is still no explanation for why it works one way on breadboard and another way on PCB!
     
  9. whit3rd

    whit3rd Guest

    Check to be sure you've connected all the unused inputs; the extra capacitance of
    a protoboard can mask floating-input issues.
     
  10. Guest

    One explanation is that you misidentified a timing capacitor or resistor for the 555 astable on the proto-board and it is oscillating at a much higherfrequency there.
     
  11. Guest

    It's *only* the problem stage that I have rebuilt on protoboard; it's stillbeing fed by the output from the last good stage of the rat's nest.
     
  12. Guest

    You mean unused OUTputs, surely? There's only one clock input line. But if you DO mean unused outputs (pins 1 through to 7) they're not connected to anything; I just cut their leads off to save having to drill extra holes that wouldn't be used anyway. I'm guessing it's safe to leave unused outputs floating, right? They don't have to be grounded or whatever do they?
     
  13. Guest

    You need to make more quantitative observations. Telling us the final output pulse is "far too long" doesn't cut it. At your clock frequency the finalstage outputs are supposed to be high for 100 seconds, and they're supposed to last high until the next clock pulse comes along. How long are they high now and how long do you want them to stay high? It may have been the rats nest was in error, it's really easy to get unwanted cross-coupling into inputs with messy wiring, so the last stage in the rats nest could be getting double triggered on its clock input.
     
  14. Guest

    Oh, I wasn't aware of that. I've just basically 'plugged' the output of one4017 into the input of the next with no pull-down resistors at all; never occurred to me that might be necessary, quite honestly. I'll modify accordingly. Hopefully that might fix that aspect of the problem.
    Many thanks!
     
  15. Guest

    I see. Well obviously I've made a fundamental mis-assumption about how these chips work. I'd assumed the pulse duration (the ON state)would remain thesame throughout the chain of 4017s and that only the OFF time *between* them would increase. Clearly from what you say that's not what happens. So basically if I want to end up with say one, one second long 'high' on the final output after a delay of 7 days (for example) I need to back calculate sothe first pulses from the 555 have a much shorter ON duration than 1 second. That's what your suggested mod is designed to do, I guess? I can see that now. Many thanks for the clarification.
     
  16. Rocky

    Rocky Guest

    Only the unused inputs need pullups or pulldowns. If they are connected to a permanently enabled output then they don't need them.
     
  17. Guest

    All the 'reset' pins in the chain of 4017s I have tied to ground via 10k resistors. Looks like another thing worth investigating....
     
  18. Guest

    On Tuesday, 11 December 2012 15:36:58 UTC+1, John Fields wrote:

    OK. Thanks for the datasheet link. The sheets I've seen up until now have been very terse affairs, badly photocopied and hard to see. This one is way more informative.
    I'm not in a position to post a schematic at this time, but from what you said in your last post it wouldn't assist much if the chips I'm using are wrong.

    Basically all I want to do is make up a time-lock for a cash safe. After a 7 day delay during which the safe remains locked shut, one timed pulse of 1second releases its electromagnetic lock and the safe can be opened. Obviously that pulse if it's from CMOS will need to be beefed up to actuate the lock, but that's the easy bit.
    Why are 4017s not suitable for the timing part of the application?
     
  19. Guest

    Many thanks, John!
    I haven't studied your circuit in detail yet, so may have to ask for clarification on a few things, but it sounds good by your description. I'm not the least concerned with a 1% error; it can be out by up to 12hrs either way as far as I'm concerned and would still be absolutely fine for my purposes.

    Thanks again.
     
  20. Guest

    Very good point- one of the most accurate long duration timebases available for applications like this is the power line. You should get +/- a few seconds accuracy over a seven day interval. The OP really needs something like this:
    http://www.intersil.com/en/products/timing-and-digital/rtcs/real-time-clocks/ISL12032.html
    There he has provisions for battery backup and external crystal timebase to coast through black/brown-outs. It can't miss. The drawback is it needs a controller, but it's worth the effort for the vastly improved performance over what he has now.
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-