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4013 question

Discussion in 'Electronic Basics' started by eatmorepies, Apr 4, 2012.

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  1. eatmorepies

    eatmorepies Guest

    I want the D type latch (using CMOS 4013) to remember a momentary signal and
    output high. When the momentary signal arrives a second time I want the
    output to drop low.

    The input signal (from sensor circuit) goes high when the light sensor is
    shadowed (checked with logic probe), this is connected to the clock - pin 3.

    Q (pin 1) connected to a 1k resistor in series with an LED to zero volts.

    Not Q (pin 2) connected to data - pin 5.

    Set (pin 6) and reset (pin 4) connected to pin 7 - Vss.

    Pin 14 is Vcc at 10V.

    As I shadow or illuminate the sensor the output of the sensor circuit goes
    high or low as required. I'm using an op-amp as a comparator.

    Q remains high all the time - irrespective of the clock signal going low,
    high, low. The LED is always on. Not Q remains low at all times.

    Looking at Q with the logic probe as the clock goes high there is a
    monentary pulse but the output still stays high. Looking at not Q there is a
    momentary pulse when the clock goes high but the output still stays low.

    The signals are the same when I remove the load (the LED) from the 4013.

    Why don't Q and not Q swap levels when the clock goes high?

    John
     
  2. What did you connect to the D input? It should be connected to not Q to get
    the required memory function.

    petrus bitbyter
     
  3. eatmorepies

    eatmorepies Guest

    Sorry - forgot to mention I had connected pin7 to 0V.

    I've just tried again with the inputs of the second Dtype grounded - R, S,
    Clk and D. No change in the circuit's behaviour.

    John
     
  4. eatmorepies

    eatmorepies Guest

    I don't know because I don't have a scope. I'm guessing the pulse flash on
    the logic probe tells me the clock signal isn't clean.

    I'm not sure what this means. I have a 0.1 microF ceramic decoupling
    capactior across the power supply.
    I think you're right.

    Would a Schmitt nand (4093) configured an an inverter be sufficient to
    de-bounce the signal? if not what do you suggest?

    John
     
  5. eatmorepies

    eatmorepies Guest


    I've just tried the 4093 Schmitt NAND (I put 2 inseries to make a Schmitt
    AND), The circuit is much improved and it switches states cleanly about 8 of
    10 times.

    Now. How to make the initial pulse last longer using some kind of monostable
    with a delay before it falls back to it's stable state?

    John
     
  6. Jasen Betts

    Jasen Betts Guest

    an easy way to do that with what you have is to put a R-C low-pass
    filter between the two schmitt NAND stages.


    ______ ______
    .--| __ \ .--| __ \
    ---+ | _// )O---[100K]---+------+ | _// )o---
    `--|______/ | `--|______/
    ===
    | 100nF
    0V--+--
     
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