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4-to-16 line decoder

Discussion in 'Electronic Design' started by Mike, Feb 23, 2006.

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  1. Mike

    Mike Guest

    I'm in a digital logic class and am having a bit of a problem figuring out a
    problem. I'm not looking for an answer, per se, but would greatly appreciate
    any good advice or links that will help me understand how to piece
    everything together. The question calls for making a 4-to-16 line decoder
    from five 2-to-4 line decoders. The book we are using is terrible.

    Thanks.

    Mike
     
  2. You'll need four decoders for the 16 outputs.

    Hint: they probably have another input, beyond the 2 select input
    lines.
     
  3. Mike

    Mike Guest

    Initially that was my thinking, but I'm not sure where the fifth decoder
    comes into play. I neglected to mention that the problem needs to include an
    enable, so maybe that's where. As far as principles go, I understand what
    they do and that they're "chained" together, but it's the "chaining"
    together that has me lost.

    Mike
     
  4. Mike,

    Assuming your 2-to-4 line decoders have output enables, you should be
    able to cascade them. Take a look at the data sheet for the 74XX139.
    Connect one of the decoders to two address bits with its enable pulled
    low and connect its four outputs to the enables of four cascaded 2-to-4
    line decoders with their address bits all connected to the other two
    address lines.
     
  5. PeteS

    PeteS Guest

    or put another way, 4 decoders to decode to outputs and 1 decoder to
    decode which output decoder to enable

    Cheers

    PeteS
     
  6. John Fields

    John Fields Guest

    ---

    +-----+
    | Y1|------------->OUT1
    +------|A0 Y2|------------->OUT2
    | +----|A1 Y3|------------->OUT3
    | | +--|E Y4|------------->OUT4
    | | | +-----+
    | | +-----------------+
    | | +-----+ |
    | | | Y1|--------|---->OUT5
    +-|----|A0 Y2|--------|---->OUT6
    | +----|A1 Y3|--------|---->OUT7
    | | +--|E Y4|--------|---->OUT8
    | | | +-----+ |
    | | +---------------+ |
    | | +-----+ | |
    | | | Y1|------|-|---->OUT9
    +-|----|A0 Y2|------|-|---->OUT10
    | +----|AI Y3|------|-|---->OUT11
    | | +--|E Y4|------|-|---->OUT12
    | | | +-----+ | |
    | | +-------------+ | |
    | | +-----+ | | |
    | | | Y1|----|-|-|---->OUT13
    IN1>---------------+-|----|A0 Y2|----|-|-|---->OUT14
    IN2>-----------------+----|A1 Y3|----|-|-|---->OUT15
    +--|E Y4|----|-|-|---->OUT16
    | +-----+ | | |
    +-----------+ | | |
    +-----+ | | | |
    | Y4|--+ | | |
    IN3>----------------------|A0 Y3|----+ | |
    IN4>----------------------|AI Y2|------+ |
    Vcc ---|E Y1|--------+
    +-----+
     
  7. Mike

    Mike Guest

    Thanks, John... that looks like a great schematic, but I guess I was hoping
    to learn more about how to come up with a solution.

    Mike
     
  8. I agree. Well done Jon.

    The only thing that I would add is that often, the function blocks you
    encounter in real parts often have inverted inputs or outputs so you
    have to add inverters here or there to get things to match up. For
    example the enable input and the decoded outputs are active low in the
    74X139.
     
  9. John Fields

    John Fields Guest

    ---
    Since the OP doesn't seem to be dealing with real parts at the
    moment, Jon's use of positive true logic throughout to _illustrate
    the principle_ is, IMO, exemplary.

    Just a nice, straightforward description of "This is how it works"
    without throwing in a lot of confusing glue logic.
     
  10. Rich Grise

    Rich Grise Guest

    ;-)

    Cheers!
    Rich
     
  11. PeteS

    PeteS Guest

    I must agree - the use of active low outputs can be *very* confusing to
    students who are trying to grasp a principle (I speak from experience
    here, having taught such things). Get the principle, then add the
    little 'features' that are there for historical and practical reasons.
    Someone mentioned using programmable logic. In this particular original
    question, it can make everything quite clear

    (I could have used case statements below, but I wanted to make the
    logic clear)

    Let's define a 2 - 4 line decoder with a select input

    module 2_4_decoder
    (
    inA,
    inB,
    out0,
    out1,
    out2,
    out3,
    select
    );
    input inA, inB, select;
    output out0, out1, out2, out3;

    always @(inA or inB or select)
    begin
    if(select) // only set outputs active if selects active
    begin
    if(!inA & !inB)
    begin
    out0 = 1'b1;
    out1 = 1'b0;
    out2 = 1'b0;
    out3 = 1'b0;
    end
    else if (inA & !inB)
    begin
    if(!inA & !inB)
    begin
    out0 = 1'b0;
    out1 = 1'b1;
    out2 = 1'b0;
    out3 = 1'b0;
    end
    else if (!inA & inB)
    begin
    begin
    if(!inA & !inB)
    begin
    out0 = 1'b0;
    out1 = 1'b0;
    out2 = 1'b1;
    out3 = 1'b0;
    end
    else if (inA & inB)
    begin
    if(!inA & !inB)
    begin
    out0 = 1'b0;
    out1 = 1'b0;
    out2 = 1'b0;
    out3 = 1'b1;
    end
    end
    else begin // select not active, deselect all outputs
    out0 = 1'b0;
    out1 = 1'b0;
    out2 = 1'b0;
    out3 = 1'b0;
    end

    endmodule

    now let's define a 4-16 line decoder, using our previous decoder, in
    the same sense as the original question, with a master select

    module 4_16_decode
    (
    in[3:0], // do this as a subscripted object to save space
    out[15:0],
    select
    );

    input in[3:0];
    output out[15:0];
    input select;

    // instantiate 5 different instances of our 2-4 line decoder and hook
    it up

    wire decode0;
    wire decode1;
    wire decode2;
    wire decode3; // decode which decoder to use

    2_4_decoder decode_decoder // to decode which decoder
    (
    ..inA(in[2]),
    ..inB(in[3]),
    ..out0(decode0),
    ..out1(decode1),
    ..out2(decode2),
    ..out3(decode3),
    ..select(select)
    );

    // now the actual output decoders

    2_4_decoder decode_low4 // lowest four bits
    (
    ..inA(in[0]),
    ..inB(in[1]),
    ..out0(out[0]),
    ..out1(out[1]),
    ..out2(out[2]),
    ..out3(out[3]),
    ..select(decode0)
    );

    2_4_decoder decode_4_7 // bits 4 through 7
    (
    ..inA(in[0]),
    ..inB(in[1]),
    ..out0(out[4]),
    ..out1(out[5]),
    ..out2(out[6]),
    ..out3(out[7]),
    ..select(decode1)
    );


    2_4_decoder decode_8_11 // bits 8 through 11
    ..inA(in[0]),
    ..inB(in[1]),
    ..out0(out[8]),
    ..out1(out[9]),
    ..out2(out[10]),
    ..out3(out[11]),
    ..select(decode2)
    );

    2_4_decoder decode_12_15 // bits 12 through 15
    (
    ..inA(in[0]),
    ..inB(in[1]),
    ..out0(out[12]),
    ..out1(out[13]),
    ..out2(out[14]),
    ..out3(out[15]),
    ..select(decode3)
    );


    endmodule


    Hope that helps too!

    Cheers

    PeteS
     
  12. It would, but only if it were in VHDL. :p

    Seriously, I would have started with a simpler Verilog version of the
    2to4:

    module decode_2_4( ENA, A, Y );
    input ENA;
    input( 1:0 ) A;
    output( 3:0 ) Y;
    reg( 3:0 ) Y;
    reg( 2:0 ) ENA_A;
    always @( ENA or A ) begin
    case( {ENA,A} )
    3'b 100: Y= 4'b 0001;
    3'b 101: Y= 4'b 0010;
    3'b 110: Y= 4'b 0100;
    3'b 111: Y= 4'b 1000;
    default: Y= 4'b 0000;
    endcase
    end
    endmodule;

    Less wear and tear on the brain, I think, if I got that right.

    Could do a for() loop and that might be better for a generic decoder
    module using parameters.

    But all this side-tracks from what the OP needed, I suspect.

    Jon
     
  13. Woops... just:

    endmodule

    without the semicolon. Oh, well.

    Jon
     
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