Full schematic
OK, here's the full schematic of my suggested design.
I'm reposting the first two blocks (the highest RSSI detector and the video switcher) because I've made some small changes to them. The circuit description in my earlier post still applies.
Here are the remaining three sections of the design.
The prioritiser deals with the problem of multiple "highest RSSI" outputs being on simultaneously. It converts the four signals from the highest RSSI detector module (actually, it only needs three of them) into a two-bit binary number that represents the number of one of the highest RSSI receivers.
The behaviour of the outputs in relation to the inputs is described in text on the diagram. The upshot is that the number represented by the output bits is always a receiver that has a highest RSSI indication, except during startup when the highest RSSI has not yet been determined.
You can draw up a truth table for the sixteen combinations of the four inputs, and check that the outputs are correct for every possible combination.
This module is the synchroniser. It detects vertical synchronisation pulses in the selected video signal and latches the two-bit binary receiver number in a CD4013 dual flip-flop. This number is only allowed to change during vertical retrace, and periodically if the sync separator stops detecting sync. (This would happen if the transmitter fails, for example, and no receivers can produce a valid video signal.)
Here is a simplified circuit description.
U4 is an LM1881N application-specific linear IC that is designed to extract sync information from a composite video signal in either NTSC, PAL or SECAM format. It receives its signal from VIDOUT, the chosen receiver signal. It generates a short low pulse on its VSYNC output during each vertical sync pulse. During this time, there is no video displayed on the monitor, so it is safe to change receivers without disturbing the picture.
The LM1881 can operate from a 12V supply but 8V is plenty and there is an 8V rail available, so I chose to use that.
U5D and U5E are connected as a latch. This latch controls the discharge of CFT (field timeout capacitor) and the clocking of U6, the selection latch. Normally U5E's output, and U5D's input, are low. The field timeout capacitor and related circuitry are used so that if the vertical sync pulses from U4 cease, due to loss of the signal, the circuit will continue to clock U6 periodically. If it didn't do this, the last selected receiver would remain selected indefinitely, regardless of any new RSSI information.
The start of each vertical sync pulse causes a positive transition on QVS's drain; this is coupled through the capacitor and diode into U5D's input and sets the latch. This turns on QFT, which discharges CFT, resetting the field timeout. After about 100 us, the capacitor on U5C's input reaches U5C's input threshold, and U5C's output goes low and pulls U5D's input low, turning off the latch. So in response to each vertical sync pulse, QFT is turned on for about 100 us, long enough to fully discharge CFT.
In between sync pulses, CFT charges up through RFT. If pulses stop, after a delay of at least 20 ms (typically 25~35 ms) (longer than the longest possible field time), U5F's output goes low, pulling U5E's input low and setting the latch again, causing a new pulse on U6's clock inputs.
U6 is a clocked latch. On every rising edge on its clock inputs (pins 3 and 11) it samples the levels on HRB0 and HRB1, the two bits from the prioritiser that identify the receiver with the highest RSSI. The latch outputs are SB0 and SB1, which feed the selection expander.
The selection expander expands a two-bit binary number (SB0 and SB1) into four indivual active-high selection signals for the four video switches in the MAX4545 in the video switcher block.
I have shown two alternative circuits. U7 is a CD4555B or HCF4555B dual two-to-four decoder with active high outputs; it is perfect for this application, but it is not widely available. I had never heard of it until I looked for a CMOS 4000-series device that would do this particular function. It is probably very little-used and will probably be on "pending discontinuation" lists, so it may not be wise to design it in.
The alternative circuit uses the two remaining spare gates in U5, and another IC, to perform the same function. These ICs are still fairly widely used. The four NOR gates from U8 each respond to a different combination of the two-bit binary number, and drive their outputs high (to enable the appropriate video switch) only when that binary number matches the combination they have been wired for.
If you use the CD4555 option, you must connect the inputs of the two unused gates in U5 to the ground or +12V rail (it doesn't matter which), otherwise they will float and pick up noise, which can cause problems.
As you see, I have assumed that your video feed is NTSC, PAL or SECAM. If that's not the case, I will need more information about the video signal. The LM1881 sync separator has some flexibility - the RSET resistor can be changed to accommodate different vertical sync intervals.
If you decide this project is too difficult, don't worry. I've enjoyed designing it, and the design (or parts of it) may be useful to other people.
Important note. I have not tested any of this design! If you go ahead with it, please send me a PM so we can keep in touch during the testing phase.
