Connect with us

3T DRAM Cadence design

Discussion in 'General Electronics Discussion' started by Design2016, Oct 22, 2016.

Scroll to continue with content
  1. Design2016

    Design2016

    1
    0
    Oct 22, 2016
    Hi.

    My question is:

    Why High value of signal OUT drop down when signal for read information is logical "1".
    The signal OUT drop for about 0.7 V. That is case when is treshold voltage lower (bulk and sours is connected together -mosfet with line of information and write line)-that we need to get higher value of OUT (logical 1).

    When I use normal shematic without connecting bulk and sours , OUT signal is not sensitive when is read signal is active.
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-