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3D Circuitry

Discussion in 'Electronic Design' started by Jon Slaughter, Oct 9, 2009.

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  1. Why are circuits not layed in 3D to produce fast amounts of gates? If you
    take your average memory circuit such as SRAM and "layer" it as high as it
    is wide then you'll get a huge increase.

    What is the difficulties in doing such things? I imagine heat dissipation
    would be a big problem but maybe one can add in "heat pipes" to carry the
    heat from the inner layers. If one has a matrix of 1000x1000 cells for a 1Mb
    memory then repeating that in the "z" dimension would give a 1Gb
    memory.(sure it would be square and bulky but thats not the point)

    Now maybe they already do this to some degree but I've never seen it
    mentioned. Maybe it's difficult to layer the substraits together?

    I was thinking that a true 3D method would be optimial for density reasons.
    If a potential solid substance could be created where one could apply a
    laser of difficult wave lengths to get different properties such as a
    conductor or semi-conductor then one might be able to make truely 3D
    circuits. Similar to 3D printing. The laser heats the material in such a way
    as to turn it into a conductor or semiconductor. It is built up in a
    continuous manner. Anyways... just an idea. Not saying it is practical but
    just the abstract idea would work.

    But I don't even see devices that use true "layering" techniques. I do
    realize that in some sense standard semiconductor fabrication uses
    "layering" but they only have one substrate layer? If one could layer, say,
    fpga cores then they would become vastly more powerful.

    Anyways, just something I was wondering about...
     
  2. GM

    GM Guest

    http://en.wikipedia.org/wiki/Three-dimensional_integrated_circuit
     
  3. krw

    krw Guest

    The last IC I worked on had ten levels of metal and a set of masks was
    north of 2$M. That was in 90nM and they're down to 40nM now (two full
    generations later). My last (and most likely next) product was on six
    layer FR4. ;-)
     
  4. krw

    krw Guest

    Cooling is the #1 reason. Memory could be stacked but the cost is
    against you there. Memory has to be *cheap*, even in expensive
    applications.
     
  5. krw

    krw Guest

    Gene Amdahl started Trilogy, which was supposed to build a WS system
    many moons ago. There was also WSI. ;-)
    Couple of years (mid '80s). He folded shop on WSI and started
    building VAX clones. Some come down form building very successful IBM
    clones.
     
  6. Memory stacking should not be too hard, say with one layer for each
    bit plane. The address, Chip select, R/W and power lines are in
    parallel, so arranging the vias or edge connectors should be easy. The
    only signals needing special handling is the data in/out pins.

    Some hobbyists used to piggyback RAM memories in DIP packages, solder
    address etc. lines together and only wire wrap the data lines :). I
    guess it had been easier to bend the DIP pins horizontally and then
    use some small vertical Vero-board strips to connect the address lines
    and then only wire wrap the data lines separately.

    Paul
     
  7. IIRC he spent some $300m on the failed process, and that was a lot of
    money back then :)

    --
    Dirk

    http://www.transcendence.me.uk/ - Transcendence UK
    http://www.theconsensus.org/ - A UK political party
    http://www.blogtalkradio.com/onetribe - Occult Talk Show
     
  8. krw

    krw Guest

    Leaky, for sure. Particularly the 0Vt transistors. It is a bit
    mind-bending to realize that one can make precision voltage dividers
    out of gate tunneling currents. ;-)
     
  9. krw

    krw Guest

    IT's not hard, just expensive. Expensive isn't done much, which makes
    it much more expensive.
    It wasn't just hobbyists. Stacked memory was a standard product in
    the '80s. The two chips had /CS bonded out to different pins (the
    adjacent pin was a NC on the standard part). It can be and was done,
    it's just expensive (so it's not done much, making it...).
     
  10. Charlie E.

    Charlie E. Guest

    There is also package scale integration, where multiple chips are
    wired together inside the package, often involving stacking one on top
    of the other and wirebonding in three dimensions. Was working with
    that tool at Cadence before the axe...

    Charlie
     
  11. krw

    krw Guest

    It was only driven to church on Sunday by a little old lady, huh? ;-)
     
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