3D Circuitry

[Jon Slaughter]

Why are circuits not layed in 3D to produce fast amounts of gates? If you
take your average memory circuit such as SRAM and "layer" it as high as it
is wide then you'll get a huge increase.

What is the difficulties in doing such things? I imagine heat dissipation
would be a big problem but maybe one can add in "heat pipes" to carry the
heat from the inner layers. If one has a matrix of 1000x1000 cells for a 1Mb
memory then repeating that in the "z" dimension would give a 1Gb
memory.(sure it would be square and bulky but thats not the point)

Now maybe they already do this to some degree but I've never seen it
mentioned. Maybe it's difficult to layer the substraits together?

I was thinking that a true 3D method would be optimial for density reasons.
If a potential solid substance could be created where one could apply a
laser of difficult wave lengths to get different properties such as a
conductor or semi-conductor then one might be able to make truely 3D
circuits. Similar to 3D printing. The laser heats the material in such a way
as to turn it into a conductor or semiconductor. It is built up in a
continuous manner. Anyways... just an idea. Not saying it is practical but
just the abstract idea would work.

But I don't even see devices that use true "layering" techniques. I do
realize that in some sense standard semiconductor fabrication uses
"layering" but they only have one substrate layer? If one could layer, say,
fpga cores then they would become vastly more powerful.

Anyways, just something I was wondering about...

 

[GM]

Why are circuits not layed in 3D to produce fast amounts of gates? If you
take your average memory circuit such as SRAM and "layer" it as high as it
is wide then you'll get a huge increase.

What is the difficulties in doing such things? I imagine heat dissipation
would be a big problem but maybe one can add in "heat pipes" to carry the
heat from the inner layers. If one has a matrix of 1000x1000 cells for a 1Mb
memory then repeating that in the "z" dimension would give a 1Gb
memory.(sure it would be square and bulky but thats not the point)

Now maybe they already do this to some degree but I've never seen it
mentioned. Maybe it's difficult to layer the substraits together?

I was thinking that a true 3D method would be optimial for density reasons.
If a potential solid substance could be created where one could apply a
laser of difficult wave lengths to get different properties such as a
conductor or semi-conductor then one might be able to make truely 3D
circuits. Similar to 3D printing. The laser heats the material in such a way
as to turn it into a conductor or semiconductor. It is built up in a
continuous manner. Anyways... just an idea. Not saying it is practical but
just the abstract idea would work.

But I don't even see devices that use true "layering" techniques. I do
realize that in some sense standard semiconductor fabrication uses
"layering" but they only have one substrate layer? If one could layer, say,
fpga cores then they would become vastly more powerful.

Anyways, just something I was wondering about...

http://en.wikipedia.org/wiki/Three-dimensional_integrated_circuit

 

[Jon Slaughter]

http://en.wikipedia.org/wiki/Three-dimensional_integrated_circuit

Cool. While I don't consider that true 3D it is probably as close as we are
going to get.

 

[Dirk Bruere at NeoPax]

In recent processes, the gates are much faster than the wiring, so
making the interconnects shorter is a big win, if you can afford it and
cool it.

Cheers

Phil Hobbs

The other perennial is wafer scale integration.

--
Dirk

http://www.transcendence.me.uk/ - Transcendence UK
http://www.theconsensus.org/ - A UK political party
http://www.blogtalkradio.com/onetribe - Occult Talk Show

 

[krw]

A typical analog chip has _22_ mask steps... pretty much equivalent to
"layers".

The last IC I worked on had ten levels of metal and a set of masks was
north of 2$M. That was in 90nM and they're down to 40nM now (two full
generations later). My last (and most likely next) product was on six
layer FR4. ;-)

 

[krw]

1. Cost. Each layer of transistors requires a separate wafer. Each
wafer is an opportunity for yield loss. Each one requires
through-silicon vias, which are also expensive. And getting all those
gates connected to the outside world by way of a two-dimensional ball
array requires a huge number of vias from upper layers. One of the
limitations on skyscraper size is that eventually all the floor space is
taken up by elevators. Same problem here.

2. Cooling. It's hard enough cooling processors as it is. Memory
isn't as bad, but it isn't 100 times easier. Many-layer sandwiches
containing lots of oxide and low-K dielectric are a huge problem thermally.

Cooling is the #1 reason. Memory could be stacked but the cost is
against you there. Memory has to be *cheap*, even in expensive
applications.

 

[krw]

Wasn't there a computer maker that bragged about WSI?

Gene Amdahl started Trilogy, which was supposed to build a WS system
many moons ago. There was also WSI. ;-)

And how long did they last before going under?

Couple of years (mid '80s). He folded shop on WSI and started
building VAX clones. Some come down form building very successful IBM
clones.

 

[Paul Keinanen]

Cooling is the #1 reason. Memory could be stacked but the cost is
against you there. Memory has to be *cheap*, even in expensive
applications.

Memory stacking should not be too hard, say with one layer for each
bit plane. The address, Chip select, R/W and power lines are in
parallel, so arranging the vias or edge connectors should be easy. The
only signals needing special handling is the data in/out pins.

Some hobbyists used to piggyback RAM memories in DIP packages, solder
address etc. lines together and only wire wrap the data lines . I
guess it had been easier to bend the DIP pins horizontally and then
use some small vertical Vero-board strips to connect the address lines
and then only wire wrap the data lines separately.

Paul

 

[Dirk Bruere at NeoPax]

Gene Amdahl started Trilogy, which was supposed to build a WS system
many moons ago. There was also WSI. ;-)


Couple of years (mid '80s). He folded shop on WSI and started
building VAX clones. Some come down form building very successful IBM
clones.

IIRC he spent some $300m on the failed process, and that was a lot of
money back then

--
Dirk

http://www.transcendence.me.uk/ - Transcendence UK
http://www.theconsensus.org/ - A UK political party
http://www.blogtalkradio.com/onetribe - Occult Talk Show

 

[krw]

I have occasionally gotten down to 180nm for analog (PLL's), but it's
(and smaller feature sizes) really pretty crappy for decent analog
functions... horrible channel-length modulation, and leaky :-(

Leaky, for sure. Particularly the 0Vt transistors. It is a bit
mind-bending to realize that one can make precision voltage dividers
out of gate tunneling currents. ;-)

 

[krw]

Memory stacking should not be too hard, say with one layer for each
bit plane. The address, Chip select, R/W and power lines are in
parallel, so arranging the vias or edge connectors should be easy. The
only signals needing special handling is the data in/out pins.

IT's not hard, just expensive. Expensive isn't done much, which makes
it much more expensive.

Some hobbyists used to piggyback RAM memories in DIP packages, solder
address etc. lines together and only wire wrap the data lines . I
guess it had been easier to bend the DIP pins horizontally and then
use some small vertical Vero-board strips to connect the address lines
and then only wire wrap the data lines separately.

It wasn't just hobbyists. Stacked memory was a standard product in
the '80s. The two chips had /CS bonded out to different pins (the
adjacent pin was a NC on the standard part). It can be and was done,
it's just expensive (so it's not done much, making it...).

 

[Charlie E.]

Wasn't there a computer maker that bragged about WSI?
And how long did they last before going under?

There is also package scale integration, where multiple chips are
wired together inside the package, often involving stacking one on top
of the other and wirebonding in three dimensions. Was working with
that tool at Cadence before the axe...

Charlie

 

[krw]

I scrapped one of Amdahl's IBM clones. One of the few large systems
that impressed me with the design. It was used for the 'Honor Card' ATM
system which was based in Tampa Florida. It was also the cleanest system
I ever saw. A lot of real IBM & Unisys systems had to be hosed down on
the loading dock to get rid of the dust & mold.

It was only driven to church on Sunday by a little old lady, huh? ;-)