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32MHz clock buffer and divider

Discussion in 'Electronic Design' started by [email protected], Apr 12, 2007.

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  1. Guest

    Hello all,
    I have a nice 32MHz 3.3V CMOS 50% duty cycle clock, and I'd like a /2
    and a /1 copy with less than +/-1ns skew between rising edges. Of
    course I can stick the clock into a 74vhc74 strapped as a /2, but how
    do I get a buffered copy with the same tpd and low skew? Is there a
    way to find an inverter or a buffer in the other flip flop in the 74
    My brain is kind of burnt right now (flu + overwork), do you think if
    I use tinylogic parts, 1 flip flop and 1 buffer, I can get a tpd and
    skew matched to each other across a 5% variation in supply and 10C to
    50C temp range, even though it's two chips?
    I just wanna know real quick so I can order parts on Digikey for the
    weekend, hopefully by then I'll be able to read datasheets again
  2. Reading datasheets you'd know that propagation delays always have wide
    margins. So you can't count on it for achieving a well specified delay. The
    only thing I can think up right now is to multiply the frequency by two.
    Then use a divide by two and a divide by four counter to get the frequencies
    you need. Make sure both the output flipflops reside in the same package.
    It's the best chance that delays and temperature dependencies are the same
    for them, so the clocks will be as synchronous as can be.

    petrus bitbyter
  3. jasen

    jasen Guest


    build your /2 from gates and then force the /1 through a similar path

    should give excellent temperature stability etc.

  4. joseph2k

    joseph2k Guest

    Personally, i recommend looking at clock driver chips.
  5. Joop

    Joop Guest

    Perhaps feed the clock to two gates from the same 74AC86 (XOR) and
    make one invert and the other not.


  6. Guest

    as long as the Clk to Q in the two output flops track I guess this
    could work,

    +---|D Q|
    | | |
    | +-|C Qb|----+
    | | +----+ |
    | |
    | +----+ |
    +--| X | | Fin*2
    | O |--+-------------+
    Fin-------+--| R | |
    | +----+ |
    | | +----+
    +------------------------|--|D Q|------- Fin_div1
    | | | |
    | +--|C Qb|
    | | +----+
    | +--------+ |
    | | +----+ | | +----+
    | +-|D Q| | +--|--|D Q|------- Fin_div2
    | | | | | | | |
    +-----------|C Qb|-+--+ +--|C Qb|
    +----+ +----+

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