Connect with us

3 JK FF in Counter Circuit - Count Sequence = 3, 1, 2, 6, 4

Discussion in 'General Electronics Discussion' started by TNC5097, Dec 3, 2015.

Scroll to continue with content
  1. TNC5097


    Dec 3, 2015
    I have the following count sequence 3, 1, 2, 6, 4. I am trying to design a counter circuit to generate this count with NI Multisim. I have attached my supporting data (i.e. state diagram, present state table, and K-maps). Please, if there is any help and/ or tips you can give me, it would be greatly appreciated. I have also attached my current standings with NI Multisim. Thank you for your time.
    Circuit Info.jpg
    Circuit Info 2.jpg
  2. dorke


    Jun 20, 2015
    You have "3 invalid counts" (yellow in the pic below).
    You should prevent them.
    two approaches can be taken:
    a)Reset the counter by async Pr/Clr, on power up,
    to a valid count value.
    b) Jump the counter to any valid count in the state diagram from those un-valid states.

    I assumed a) is the case.

    Use the JK excitation table to build the required J,K for the next state of the counter.
    create the truth tables and get the Ji,Ki terms
    I showed only an example of J2,K2

    In order to get a correct BCD read from the 74LS47 you should connect the Qs of the F.F not the Q' !

    Attached Files:

    • JK.jpg
      File size:
      103.2 KB
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day