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3 dB bandwidth

Discussion in 'Electronic Design' started by [email protected], Jun 21, 2005.

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  1. Mike Monett

    Mike Monett Guest

    Promise you won't laugh:)

    2N6802 NMOS
    2N6804 PMOS

    2N2222 NPN
    2N2906 PNP

    SPICE doesn't care about breakdown voltage on these devices. Again, the
    goal at this stage is simply to evaluate different architectures. The
    mosfets show a very dramatic difference with and without the bipolar
    driver, so the driver seems a necessary part of the design. The actual
    parts selection and detailed design is still way downstream. There's
    still lots of work to look at short circuit protection, etc.

    For example, short circuit protection by current limiting doesn't seem to
    be possible in this type of follower. If the output were designed to
    limit at some fixed current, the output voltage would be limited to Imax
    * Rload. However, the input voltage could still go anywhere, which means
    the problem is transferred to the input stage, which now has to handle
    the voltage difference between input and output.

    Given that very low leakage diodes may be impossible to find, and series
    current limiting mosfets only go to about 500V, this creates a rather
    difficult issue. Perhaps limiting the input current with a large series
    resistor might work, but this increases the noise. And I still don't know
    how the op amp would cope with 1mA or so current at the input. Some of
    the datasheets show the input driven well past the supply rails, but I
    still need to test with the actual device.

    As far as fixing the SPICE models, there's several ways to go. Jim
    proposed that Level 7 might solve the problem. Also, measurements on
    working hardware might show the performance is more than adequate for the
    requirements and no further SPICE work is needed. Or bench work might
    uncover different problems that SPICE can't see.

    For example, is the op amp really capable of 1 ppm performance, and where
    do you get high value resistors with 0 ppm voltage coefficient? Will the
    oscillations show up, and will they be impossible to kill without adding
    too much resistance in series with the gates?

    So there are lots of issues. If improving the SPICE model would help
    solve these problems, then that would be the way to go. But right now, I
    don't think it would make that much difference, and I can work on the
    other problems while you and Jim sort out the modeling issue:)

    Mike Monett
  2. Mike Monett

    Mike Monett Guest

    Ha - SPICE is nice, but I much prefer actual working hardware:)

    Just to clear up possible confusion, the turnon distortion I'm talking
    about is not slew rate limiting. It is very different, and starts on the
    rising edge of the signal, not at the zero crossing where the slew rate
    is greatest. It is very sensitive to the value of the gate resistance. It
    only shows up when multiple mosfets are stacked in series.

    The waveforms change with different circuit parameters, but here's an
    example. The gate resistors are 330k. The schematic is at

    The output waveform shows all the gate voltages as VG1 through VG6. You
    can see the lower ones show the mosfet is close to saturation. Driving it
    just a bit harder puts it into saturation, with very severe distortion on
    the output signal.

    I am concerned about this since the difference between the output voltage
    and the input signal now appears at the input to the op amp and may
    damage it without protection.

    Adding complimentary bipolar drivers to the mosfet gates completely
    eliminates this problem. It also allows increasing the bias resistance
    significantly, since small 50pF caps can be added across each resistor to
    handle the transient current requirement. The load on the drivers is zero
    when the input is constant. I'm sure you could find some pathological
    signal that would introduce a small bias error, but I don't think that's

    The error would have to get very large to cause breakdown on the devices
    or cause an error in the output signal. So I expect the follower to
    handle most normal cases, which is to simply measure the dc voltage with
    very low loading.

    BTW, the circuit loading can have a significant effect. For example, most
    dvm's switch to a 10 meg input divider above some range.

    In the case of 6 or 8-digit measurements, the source impedance of the
    voltage under measurement would have to be less than 10e6/10^num for 1LSB
    error, where num is the number of significant digits in the reading.

    For example, when measuring to 6 digits at 100 volts, the source would
    have to be less than 10 ohms. However, with the 10fA input current of a
    high voltage follower, the source resistance could be (100 * 1e-6) /
    1e-14 = 1E10 ohms for the same 1LSB error.

    This is a Big difference. So the effort to develop a high voltage
    follower is definitely worthwhile. And thanks for your help!

    Mike Monett
  3. Mike Monett wrote...Mike, from my perspective, there's so much wrong with your circuit
    and reasoning, I don't know where to start - cough *class-AB bias*
    cough 2n6804?? cough *transconductance* cough *non-zero-impedances*
    cough *parasitics* cough *slew-rate* cough - cough. Clears throat.

    Instead of writing a tome, I'd better attack the thick ferrite-core
    transformer folder I brought home, trying to get ready for vacation.

    I'll retire to await your bench tests. Perhaps after you get some
    real-world experience with 2000V MOSFET linear amps, you'll listen
    to my advice. Or perhaps not.
  4. Mike Monett

    Mike Monett Guest

    I guess I don't follow:)

    Bear in mind, this circuit has a different purpose than conventional
    amplifiers. So the same logic and reasoning may not apply.

    What's wrong with complimentary mosfet followers? Your suggestion
    had a single class-A follower after the op amp, and you only went to
    +/- 210V. Here's your approach:
    As I mentioned previously, I would like to take advantage of the
    high impedance all the way to +/- 1KV. That is definitely going to
    have dissipation and slew rate problems with a single follower, and
    it will be hard to swing to the negative rail wthout using a very
    large resistor betwen the follower and the output inverter. This
    increases the noise.

    Bandwidth is a consideration. My approach looks like it can easily
    go to well over 1KHz. This simplifies the problem of suddenly
    applying a high voltage to the input of the circuit, such as when
    measuring the voltage on a power supply cap. A simple rc filter with
    1 meg in parallel with 5pF limits the input slew rate to well below
    what the output can handle. With your circuit, it would take a much
    longer time constant, and the setling time would be much greater.

    2N6804? Other devices behave the same fashion. All I'm concerned
    about is the architecture. It doesn't help if the SPICE model is
    accurate to the last knat if the architecture is wrong.

    non-zero-impedances? Not sure what you are referring to.
    Complimentary bipolars between the bias string and the mosfets solve
    the problem I posted earlier. This also allows less dissipation in
    the bias string. What's wrong with that?

    parasitics? Yes, known problem. SPICE is not going to help there.

    slew rate? As I illustrated, the original circuit failed long before
    slew rate became a problem. The emitter followers fixed that
    problem. What's wrong with that?

    Bench experience? Yes, I intend to do that next. But I believe SPICE
    has pointed out some severe problems that would be difficult ot
    impossible to troubleshoot on the bench. Hard to diagnose a circuit
    when the components are blown all over the lab.

    I'd like to listen to your advise. What other suggestions have you
    offered in this area, besides to model the device in SPICE?

    Have you replied to Jim's comment on using level 7? If that works,
    that would greatly simplify the problem, instead of having to modify
    every SPICE model you need to use.

    I appreciated your help. Floating the input supplies was the key to
    the cmrr problem. But +/-200V is realistic using only 1 device.
    +/-1KV is not.

    Mike Monett
  5. Mike Monett

    Mike Monett Guest

    Mike Monett wrote:

    Nevermind - I did some more research. What a mess. PSPICE Level 7, BSIM3,
    is Level 6 or Level 8 in other simulators, and has so many revisions it's
    impossible to keep them straight. A quick check showed some 340
    parameters in the model. Here's a listing from MicroCap:

    With so many parameters, it would be impractical to model a device
    from bench measurements. And the manufacturers are not going to do it
    when they can sell eveything they make now.

    So what's the solution. Your approach means measuring a device over a
    wide range, and fitting the model by trial and error until it matches the
    measurements. But the very next device will be different, won't it?

    Are accurate subthreshold models really needed? I viewed some of the
    curves posted on abse. Sure, some are pretty bad. But if they still show
    conductance below 100uA or so, does it really make that much difference?

    In a static condition, such as a follower measuring a DC voltage, the
    difference between the SPICE model and actual hardware may be some
    millivolts change in the gate voltage. The op amp would handle this
    easily. There is already considerable variation from one device to the
    next, so a design cannot rely too heavily on this parameter for correct

    The next issue is simulating dynamic operation. SPICE Level 3 does not
    conserve charge, so any simulation will be in question. Besides trying to
    model the device yourself, is there any other reasonable approach?

    I submit several things for consideration:

    1. SPICE is just a model. Use it for guidance. Don't take it too
    seriously. Real life devices also show differences from one to the next.

    2. The Sandler paper was interesting, and the graphs of various SPICE
    versions on abse at subthresholds definitely are different. But I have
    yet to see the results of an actual simulation comparing the performance
    of a circuit with incorrect subthreshold model vs accurate model. Does it
    really make that much difference in closed loop? If so, is it comparable
    to normal device variations?

    And what about the failure of Level 3 to conserve charge? Isn't it a bit
    of a futile exercise to try to adjust the dc current of the device below
    threshold, when the entire model doesn't handle the device capacitance

    In an actual large signal simulation, the device would pass through this
    region quickly and spend most of its time above the threshold. So if the
    simulation behaves for signal levels ranging from very low all the way up
    to saturation, isn't that good enough? Incidentally, I find I have to do
    this with any active circuit, not just mosfets.

    Maybe we should just go to a table entry for mosfets:)

    Mike Monett
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