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24-bit 100kHz A-D converter with optical output

Discussion in 'Electronic Design' started by Winfield Hill, Sep 18, 2005.

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  1. I'm back to finalizing my design for a "dual 24-bit 100kHz A-D
    converter with optical s/p-dif output," after taking some time
    away to struggle with refining a PCB design for a 400MHz 14-bit
    precision balanced DDS generator for the same project.

    My 24-bit A/D design was "completed," with its schematic captured
    and edited to maturity a few weeks ago, and now I'm back working
    on it, ready to pre-position the parts on the PCB before sending it
    to my layout gal. So the time for making any changes is rapidly
    coming to a close, and I find my confidence is faltering. Have any
    of you folks done any designs with these new-fangled 24-bit delta-
    sigma converters, and if so did you learn anything I should know?

    http://www.cirrus.com/en/products/pro/detail/P1024.html
    http://www.cirrus.com/en/products/pro/detail/P1009.html

    I'm using the Cirrus-Logic cs5381 and cs8406 chips, operated from
    a well-filtered and bypassed 5V linear supply, using 3.3V logic,
    and driving the A/D balanced inputs with balanced LT1468 opamps.
    These chips want 2700pF right on their input (!), so I'm using the
    standard high-speed opamp capacitive-load circuit.

    The 100kHz output rate is created using a 12.8MHz PLL oscillator
    working from an external stable 10MHz reference, with special care
    taken to insure a Philips 74hct9046 PLL chip is working in a quiet
    environment to reduce jitter.
     
  2. Jitter.....

    hi Win, just been looking at the DICE,cos i ran out of beer
    http://www.wavefrontsemi.com/products/DICEII/DICE_Presentation/DICEII_Presentation.pdf
    they seem to improve jitter perfomance, but it's a bit over above
    comprehension at the mo, sorry


    martin
     
  3. John Larkin

    John Larkin Guest

    Is this actually for audio? The on-board voltage reference might have
    a lot of lf noise if you want real precision. Audio doesn't matter:
    the source s/n is nowhere near 20 bits.

    Look out for magnetic pickup loops, too, espacially if there will be
    fans nearby.

    Does jitter matter much to delta-sigmas? They average a lot of events.

    John
     
  4. John Larkin wrote...
    They solve that with a filter-cap node in the reference pathway.
    No, not audio - it's a five-channel capacitance position gauge.
    But its likely 18 to 19 bits of signal robustness will suffice.
    That's a good suggestion. The environment will be magnetically
    quiet, except for a rather noisy switch-mode linear motor. :>(
    That's clearly a significant PCB-layout issue. Hmm.
    Indeed. The monster-cable crowd says it matters. I wish I knew.
     
  5. Guest

    There are very few designers who can do justice to a 24-bit converter.

    That's the bad news.

    Now for the good news..........

    There are even fewer people who can properly test a 24-bit design.

    Take your best shot. Nobody will ever be able to prove it doesn't do
    what you say it will.

    Jim "I am *not* kidding." Meyer
     
  6. John Larkin

    John Larkin Guest

    I'll second that :>(

    On the dac board we just did, the bottom range is +-25 uV full scale.
    It's VME, and there's typically a fan tray at the bottom of the
    cardcage. We got similar induction levels for 120 vac and dc brushless
    fans, in the ballpark of 1 uV per square cm of loop area for the
    channels closest to the fans, so loop area minimization was a prime
    consideration in parts placement and routing.

    You might consider filtering the power drive to the motor some. Both
    the mag field and the spikes could be nasty around low-level stuff.


    John
     
  7. Hi Win,
    We used the (pre-release) CS5372 24bit ADC with a CS3302 front end diff
    amp, a CS4373 24bit test DAC, ADG734 MUXes, and an AD780 reference.
    This was for a 10,000+ channel seismic data aquisition system.

    CS5372 http://www.cirrus.com/en/products/pro/detail/P274.html
    CS3302 http://www.cirrus.com/en/products/pro/detail/P1033.html
    CS4373 http://www.cirrus.com/en/products/pro/detail/P1042.html

    Much to the surprise of the Cirrus guys we got better performance than
    the their "reference" board in a direct A-B comparison. From memory I
    think we got typically <-126dB THD and <-130dB S-N with careful board
    layout following the usual rules. Nothing too special, just a typical 4
    layer job and keeping the digital and analog halves pysically separate.
    The device pinouts look to be designed with this in mind which was real
    handy.
    Naturally we didn't have the gear to independantly test these sorts of
    levels, but with the excellent test DAC and some signal processing it
    was able to test itself :->
    The anti-alias caps on the ADCs were fairly important, high value COGs
    were speced in the end, although good performance was still had with
    run-of-the-mill polycarbs.
    The datasheets pretty much mentioned all the "gotchas" for these
    devices, not sure what your device is like though.
    The biggest problem we had was with the instruction set and some quirky
    operational mode issues. The analog performance was spectacular from
    the first prototype, so didn't get to learn much the hard way on that
    side of things :-(
    We used Phillips 74HC4046A's for regeneration of the local clock
    (2.048MHz) from the data stream and jitter wasn't a problem.
    Local linear regs were used for the rails.

    Have fun!

    Dave :)
     
  8. David L. Jones wrote...
    Whew, did you have 10,000 A-D converters?
    Thanks for the great story, that's encouraging!
    Roger willco.
     
  9. I read in sci.electronics.design that David L. Jones <>
    How was it for EMC emissions? The Cirrus stuff often has extremely fast
    edges, which delight in escaping from whatever enclosure you put them
    in.
     
  10. Tim Shoppa

    Tim Shoppa Guest

    The 100kHz output rate is created using a
    Divide (by 100) down to 100kHz, multiply up (by 128) to 12.8MHz? Or
    divide down (by 25) to 400kHz, multiply up (by 32) to 12.8MHz?

    If jitter matters to you and you have to be PLL locked to that 10MHz, I
    would advise that you use a simple varactor-tuned LC VCO.

    Otherwise just get a 12.8MHz crystal (off-the-shelf frequency) and
    avoid all that PLL crap.

    How did your DDS PCB layout go? You didn't actually believe AD's spec
    for the size of the AD9953 die ground pad did you? :).

    Tim.
     
  11. Tim Shoppa wrote...
    That's it. Higher reference frequencies are better, right?
    Good advice, I don't know if it matters that much.
    No choice, I have to lock to an external precision time reference.
    I made it 0.20" square, with a 0.11" hole in the middle to reach
    in with a soldering iron... Crude, but... What do you suggest?
     
  12. Yeah, a big Seismic boat (for deep water oil exploration) can tow 8 or
    more "streamers" up to 8-10km in length each. Each streamer can have a
    thousand or more Hydrophone channels spaced at regular intervals. Each
    channel has to have a 24bit ADC, 24bit test DAC, and associated
    switching to allow for full testing of THD, noise, sensor capacitance,
    leakage and so on. Cost just for the front end electronics alone is in
    the order of US$100/channel.
    All the channels across all the streamers must be fully syncronised and
    sampled continously in real-time. The boats operate 24/7 for months on
    end.

    Interestingly, the system size is ultimately limited by the power
    consumption. Losses over 10km of streamer are huge, 500VDC in one end,
    <100V at the end. So the DC-DC converters for each module must operate
    over this entire range. It's all a big trade-off, more copper = more
    weight = more floation material required = bigger diameter cable = less
    total length = less streamer the boat can carry etc. Higher voltage =
    more difficult to design DC-DC converter = lower efficiency over the
    whole range etc...
    Total power consumption per channel is critical. The ADC might be only
    25mW at full bandwidth, but by the time you add everyhing else up it's
    more like 1W/channel.

    The highest performance ADCs and DACs you can get are designed
    specifically for the Seismic industry (land and marine). Cirrus are
    major players and are ADC of choice in the industry.

    Dave :)
     
  13. We didn't have to worry about any of that :p
    These are used in the ocean so no need to meet any commercial EMC
    requirements apart from it not interfering with itself.
    Sharks do like to bit them though, but we aren't sure if that's becuase
    of the emmissions or that they are simply a yellow colour :->

    Dave :)
     
  14. David L. Jones wrote...
    I'm interested in the 100-500V input DC-DC converter, what output
    voltage(s) did it have, how'd you keep it quiet enough to work with
    the 24-bit A/Ds? Was its clock synchronized with the A/D clock?
     
  15. We used a two tier power system
    1) A 100-500VDC to 12VDC converter for some global electronics, and a
    100-500VDC to 100VDC converter for phantom power on the data lines
    which connected and powered the aquisition modules.
    2) A 100VDC to 3.3VDC converter for the local aquisition digital stuff,
    and then a +3V LDO (MIC5255) for positive analog plus a switched cap
    inverter (LM2662) and -3V LDO (MAX1735) for the negative analog.

    All of the flyback converters and the switched cap inverter were
    synchronised with the telemetry clock from which the sampling clock was
    derived. So the entire system was syncronous.

    Add some physical seperation, bare bones filtering, and the balanced
    inputs on the diff amps and ADC, it wasn't a problem. No shielding was
    required.

    Dave :)
     
  16. Chris Jones

    Chris Jones Guest

    If jitter really does matter to you, then a PLL with a VCO made from a
    crystal oscillator with a varactor for fine tuning (VCXO) would be the
    quietest choice I think. To me the appeal of the VCXO PLL approach is that
    there can be quite a lot of noise or ripple on the tuning input of the VCXO
    and it still doesn't affect the output much because KVCO is so low. The
    tuning range only needs to be as large as the drift of the crystal plus the
    drift of the 10MHz reference. I would probably try to run the crystal at a
    multiple of 12.8MHz and follow that with a CMOS divider.

    Chris Jones
     
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