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2 Stage BJT (Potential Divider Biased) design

Discussion in 'Electronics Homework Help' started by bratva, Apr 20, 2016.

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  1. bratva


    Apr 20, 2016
    Hi all.

    I require help designing and analyzing the following using the parameters given below:

    Stage 1 - (Potential Divider Biased) Common Emitter: 2mA ≤ Ic(q) ≤ 15mA
    Av (CE) = 2 ≤ |Av| ≤ 6 (with RL connected)

    Stage 2 - (Potential Divider Biased) Common Collector: 5mA ≤ Ic(q) ≤ 10mA
    Av (CC) = 1 (approximately)

    *Also, RL = RC
    *Both Stages must be mid-point biased
    *Power Supply = +15V
    Last edited: Apr 20, 2016
  2. dorke


    Jun 20, 2015
    Welcome to EP.
    What is the problem you have with designing those 2 circuits?
    They are straight foreword,is this homework?
    One important issue missing is the frequency range required.
    and another issue is the value of RL .
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