# 1Mhz -> 1hz

Discussion in 'Electronic Design' started by siva, Dec 19, 2005.

1. ### sivaGuest

Hi,
to convert the 1 mhz input to 1 hz output, how many no. of D-flip flop
should i use?
Thanks
regards
siva

2. ### Fred BartoliGuest

Approximatly 19,931568569324174087221916576936

3. ### PeteSGuest

Hint for the OP

Derived, of course, as log[2](1,000,000)

PeteS

4. ### Tam/WB2TTGuest

None. Use 6 divide by 10 counters.

Tam

5. ### PeteSGuest

Actually, what I should have said is:

'This is covered in all decent [very!] basic texts. Read one'

Cheers

PeteS

6. ### Guest

If you have to ask the question, the honest answer is none - you are
highly unlikely to get it to work.

If you learnt quite a lot, you could probably do it with 21 - using 20
to make a 20-bit counter, which can count up to 1048576, and the last
one to hold the reset pulse for one period of the 1MHz clock. You'd
need quite a bit of combinational logic to persuade the D-types to act
as counters, and some more to initiate the reset pulse at a count of
999,999.

Fairly trivial if you buy your D-type bistables in a programmable logic
chip, otherwise an absolute nightmare to wire up.

7. ### PeteSGuest

If I was doing it in some programmable logic, it might look something
like

module OneHzFromOneMeg
(
out,
clk
);

output out; // 1 Hz output
input clk; // 1MHz input clk

reg [18:0] Count; // half of the count
reg FinalDiv2; // to guarantee 50% duty cycle
wire TermCount; // terminal count test

assign TermCount = (Count == 19'b1111010000100011111)? 1'b1 : 1'b0;
// detect a count at 499,999

assign out = FinalDiv2;

always @(posedge clk)
begin
if(TermCount)
begin
Count <= 0;
FinalDiv2 <= !FinalDiv2; // toggle output
end
else begin
Count <= Count+1;
end
end

endmodule

Pretty simple really, but it requires a basic knowledge of what the
counter needs to do

Of course, in a real design I would probably add a reset.

Cheers

PeteS

8. ### Keith WilliamsGuest

D <= Q-bar isn't a lot of combinatorial logic. Just do a ripple
counter, with Ck(n)<= Q(n-1) and D(n)<=Q(n).
True, if exactly divide by 1E6 is needed (5% error isn't
tollerated).
Programmable logic is the easiest way, but 8-bit counters with
the desired count to the inputs and do an and use TC to load the
count. Details left to the OP.

9. ### Guest

I've never been able to get my hands on a 579 - or any other 8-bit TTL
counter - when I've needed one. The CMOS 74HCT40103 has been much
easier to get hold of, though it doesn't have a look-ahead carry output
(but you wouldn't really need that at 1MHz.

10. ### theJackalGuest

Somebody said 20,21 flipflops .. naw you can use much less . A
typical divide by 10 counter has 4flipflops and so If you don't feel
like cracking your brains get 3 divide by 10 counters , cascade them
and you got your 1pulse/sec signal.
If you want to design the thing let me know

"Go easy on the whisky "

theJackal

11. ### Keith WilliamsGuest

Indeed, it's a little early for such.

12. ### John PopelishGuest

3 divide by 10 counters gets 1 MHz down to 1kHz.

6 divide by 10 counters gets you to 1 Hz, with 24 flip flops.

13. ### theJackalGuest

Six decades oh yeah ... I'd hope to live over that age though.
its never too late over here .

theJackal

14. ### theJackalGuest

Yes . Its been a busy day on Mixer theory here ... LOL

It seems the limit is log10^6/ log12 *4 = 22 flip flops

"Go easy on the whisky"

theJackal

15. ### Spehro PefhanyGuest

You don't need to decode the 999,999 completely, on an 'up'-only
counter it's sufficient to detect the 1's in the appropriate spots
with a 12-input AND gate. A 74CH74A @5V is fast enough to do a 1MHz
ripple counter with some margin to spare (30ns * 20 = 600ns).

But, I think I'd prefer to do a divide by 15,625 (which only requires
a 6-input AND eg. 74HC11) preceded by a divide-by-32 to give lots of
decode time, and followed by a divide-by-2 to give exactly 50% output
duty cycle @ exactly 1Hz.

Best regards,
Spehro Pefhany

16. ### Guest

Spehro Pefhany skrev:
or use a presetable counter and use carry instead of the ANDs

-Lasse

17. ### Guest

Not right.

2^20=1,048,576 - I've recommended using 21 D-type bistables so that you
can use one more D-type to stretch the reset pulse out to 1usec.

18. ### Guest

If you could find a divide-by-12 ic (they have appeared in the
data-books, but I don't recall every seeing one stocked by a
distributor), you'd still need six of them - 24 bistables.
What it really means is that you weren't thinking straight.

The real limit is still 20 bistables.
Unfortunately, I understand it all too well - as well as what you don't
say because you haven't understood the problem well enough to think it
through properly.
The question was restricted to D-type flip-flops, and I've already
indicated that I'd use one more to produce a tidy reset pulse.
Obviously, you need combinational logic to make such a counter work.
You can use propagation delays through combinational logic to produce a
reset pulse which would be very likely to be wide enough to reset all
the bistables, but since most logic families don't specify minimum
propagation delays, you can't always be absolutely confident of the
reliability of such as system. I've used delay lines to solve this sort
of problem, but they aren't cheap.

19. ### theJackalGuest

I've seen some on sale on the web
By writing log10^6/ log12 *4 = 22 flip flops
I was thinking very straight ... Math stretches right where human
intuition sometimes fails . As I said ask ... and I will explain.
By dividing by log 12 i was getting to the maximum number of mod 12
counters which would be 5. With 5 of those you'd have a frequency of
1000000Hz /2.48832000E+005 =
4.01877572E+000Hz left .
I'd easily handle that with a Mod 4 counter leaving me with
4.01877572E+000Hz/4 = 1.00469393E+000 Hz which is quite good.
Total number of flip flops = 5*4 + 2 = 22 flip flops ... which is what
my simple division of logs up there was saying.
I was acting in a subtle manner, read above ... it wasn't easy for
anyone to guess where the math was pointing to!
Regarding the delays I'd measure them before building the circuit. You
have at least 4 different types and they can amount to 10's of
nanoseconds which in terms of frequency is a lot . Mostly depend on
the technology of the logic families being used.
Then don't forget clock skews.

theJackal

20. ### Guest

But 22 flip-flops isn't quite enough, even if two of them aren't in
divide by 12 packages

I don't think you mathematical exercise took you anywhere useful
Hmm - ternary logic? I suspose there might be a way of exploiting the
fact that a tri-state output can be in three states ...

I'd love to know what you've got in mind.
Nothing complicated about where it was pointing - the puzzling aspect
was why one would want to point the OP that way.
A pretty good rule of thumb is to assume the minimum propagation delays
to be one third of the maximum delays, but if the manufacturers don't
guarantee it, it is risky to rely on it.

Measuring propagation delays before you build the circuit is sort of
okay, for a one-off. One very fast TTL system I ws involved with at
Nijmegen University relied on exactly that, and the engineer go the
system back about once a year as one of other of the ICs had aged
enough to take its propagation delay outside the acceptable envelope.

So the researchers didn't have an ESR machine for a couple of days
while he shuffled ICs until he'd got it working again. I replaced a
couple of critical components with ECLinPS and we got rid of almost a
nanosecond of pattern-related jitter, as well as the really tricky race
condition.

I essentially completed the design of a properly toleranced system,
using a lot more ECLinPS to deliver much better performance, but the
grant that ran the ESR machine dried up, so it was never built.