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10BASE-T Clock Recovery PLL

Discussion in 'Electronic Design' started by Andrew Holme, May 3, 2004.

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  1. Andrew Holme

    Andrew Holme Guest

    Just for fun, I'm trying to design a PLL for 10Mbps 10BASE-T Ethernet
    clock recovery.

    The VXCO is Kvco = 133 Hz/volt = 838 radians/volt-second. The digital
    phase detctor has a charge pump output with Kpd = 0.7 mA/radian. The
    comparison frequency is 10 MHz.

    The 10BASE-T frame has a 64 bit preamble which allows the receiver
    time to synchronise. The loop needs to lock in 6.4 micro-seconds
    demanding a wide bandwidth. My question is: how wide? 40 KHz?? The
    first quadrant of a 40 KHz sine wave is 6.25 micro-seconds.

    I'm doing Bode plots for various loop filters using C++. I don't have
    any fancy simulation software. Maybe it's time to get some??

    Worryingly, my design seems to be calling for impractical component
    values. For example, a loop filter consisting of (22pF || 180k) in
    series with 470pF has a -3dB point of only around 27 KHz.

    Is it ever going to work?

    On the plus side, the lock doesn't need to be perfect after 6.4
    micro-seconds - just good enough to recover data. Lock can only
    improve during the data bits. I don't care about phase noise.

    I wonder if I need DC steering to keep the control voltage mid-rail in
    the absense of data pulses? Without it, the phase detector will push
    the VCO down to Fmin between packets.

    Andrew.
     
  2. Jim Thompson

    Jim Thompson Guest

    See "ShiftRegisterPLL.pdf" and "SyncRingOsc.pdf" on the
    S.E.D/Schematics Page of my website.

    I've done a number of these "jerk-able phase" systems. I like them
    because they can handle missing transitions without going off into
    la-la land.

    ...Jim Thompson
     
  3. Andrew Holme

    Andrew Holme Guest

    Thank you, Allan and Terry.

    Setting Kvco much higher, I can now get wide bandwidth with sensible
    component values. I think I'll use an LC oscillator.

    To my bode plot tabulator, I've added a GUI with scroll bars to set
    component values but I really want to plot gain/phase graphically.
    That would give me a more intuitive feel for how the values interact.
    It's hard to take in columns of figures! I'll try scilab.

    I know how to evaluate stability / phase margin using bode plots, but
    I notice that some people design phase locked loops using natural
    frequency and damping factor. I have a few worked examples of this
    method in (Plessey) data books but no reference material on it. Can
    anyone recommend any good bed time reading - preferably, covering both
    2nd and 3rd order loops?

    I'm also looking for ways to estimate settling time.

    Thanks,
    Andrew.
     
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