100v chopper, was switching 400V

[AB]

Good day all,

I started this quest several months back with the goal of learning
about Spice and to design a switching circuit that I could use to
power a photomultiplier tube from a battery.

With a great deal of help from many of you (especially Winfield Hill)
I have the following circuit (posted ABSE, see below).

The driver circuit switching transistors itself draws low power, 16 to
21 ua (average) depending on the speed of the rising and falling edges
of the signal generator. This is good!

During my Spice modeling I discovered that the circuit was very nicely
optimized and that changing component values unusually resulted in
higher wasted power.

I also discovered that I don't really need to switch 300 volts to get
my desired output voltage, so the schematic below shows 105 vdc
sources instead of the original 300 vdc.

I also discovered that the output voltage from this switching circuit
does not have to be square waves with 50/50 duty cycle and it the
output voltage can have 1 to 10 us rise and fall times. My input from
the signal generator can have similar rise and fall times without
affecting the output much.

I have discovered a problem however and I'm not sure if it's fixable
however.

The problem seems to be large current spikes at the V4 power supply,
ranging from 6 to 95 ma, depending on the rise and fall times of the
signal generator. Although the spikes are short duration, the average
current output from V4 varies from 3.5 to 566 ua (depending on the
rise and fall times of the signal generator).

The highest average current output from V4 happens when the rise and
fall times of the signal generator is set to 1000 ns. I suspect that
Q2 and Q3 are conducting at the same time for a brief instant, hence
the high power consumption.

Is there any way to insure that these transistors do not conduct
simultaneously?? I was hoping to use slower rise and fall times if
possible because slower rise and fall times means lower power output
makes the input circuit waste less power.

I've posted the circuit (minus the load) in
alt.binaries.schematics.schematics, see 100v chopper title there. The
..ckt and a pdf of the schematic is posted there.

How do I minimize the current drawn because both output transistors
conducting at the same time???

Thanks,

Art

 

[AB]

Thanks much, I think your guess was pretty close, but you lost me when
you attempted to describe the fix.

I've posted the pf and the .ckt on my personal webspace, so it should
be a click away for anyone who wants to look at it.

http://www.uninets.net/~artky1k/100vchopper.pdf

http://www.uninets.net/~artky1k/100vchopper.ckt

I already have lots of R and C in the base of Q3, as you can see on
the pdf. Since my load does not need fast edges, would it be easier to
make Q3 turn off faster? Or, perhaps adding a modest sized emitter
resistor in Q3 (since my output current is small, I don't think this
would impact the output voltage amplitude much.

Take a look at the full schematic and many thanks.

Art

 

[AB]

If your circuit doesn't need fast edges, and the prblem only occurs
when the input signal dV/dT exceeds a certain value, then filter the
input signal.

OK, I have tested it with 1 ns, 10 ns, 100 ns and 1000 ns rising and
falling edges to the input.

With the 1 and 10 ns edges, the thing draws horrendously large peak
current on each transition, but the average current drawn is somewhat
reasonable.

With 100 and 1000 ns edges, the peak current is lower, but the average
current skyrockets. An examination of the power supply pulses shows
that they are smaller amplitude, but much longer duration, so the
average current is higher.

So, there appears to be a sweet spot, somewhere in the middle, where
it doesn't waste as much power.

I'd like to have it be much less susceptable to the input signal
edges, which allows for easier and less power consumed by the driver.
I need this thing to operate from batteries, so I am willing to have a
more complicated circuit in exchange for less lower power consumption.

Check that the circuit still performs as intended over the
environmental range, though.

OK.

What happens to your simulation when the two 105V sources are
connected, or only one is used? You're circuit is unlikely to function
in the real world without very close connection between the emitter of
the upper switch and its associated level-shifting drive circuitry. It
also looks very susceptible to HV supply noise, considering the
capacitive coupling methods used.

When there is only a single 105v supply, the results are the same. I
made a second supply just to drive the totem pole transistors for the
purposes of isolating and dissecting the circuit. In reality, these
will be the same single supply.

By modeling my load using a signal generator input, I've discovered
that slower rising edges produce nearly the same identical result. So,
I'd like to tune the circuit so it can be driven with slow edges in
order to take advantage of a simpler/less power hungry source to drive
the totem pole output transistors.

I also DO NOT need 50/50 duty cycle (as I had previously thought).
When I model the load with a signal generator input, I get nearly the
same results as long as the pulse is in the a 2 to 98 percent duty
cycle range.

I have not tried a traingle wave input, but my guess is that it will
work just as well.

What's the easiest method to tune this circuit to operate properly
with 1 or 2 microsecond edges (without wasting additional power)??

Thanks,

AB

 

[R.Legg]

With the 1 and 10 ns edges, the thing draws horrendously large peak

current on each transition, but the average current drawn is somewhat
reasonable.

With 100 and 1000 ns edges, the peak current is lower, but the average
current skyrockets. An examination of the power supply pulses shows
that they are smaller amplitude, but much longer duration, so the
average current is higher.

So, there appears to be a sweet spot, somewhere in the middle, where
it doesn't waste as much power.

I'd like to have it be much less susceptable to the input signal
edges, which allows for easier and less power consumed by the driver.
I need this thing to operate from batteries, so I am willing to have a
more complicated circuit in exchange for less lower power consumption.


When there is only a single 105v supply, the results are the same. I
made a second supply just to drive the totem pole transistors for the
purposes of isolating and dissecting the circuit. In reality, these
will be the same single supply.

By modeling my load using a signal generator input, I've discovered
that slower rising edges produce nearly the same identical result. So,
I'd like to tune the circuit so it can be driven with slow edges in
order to take advantage of a simpler/less power hungry source to drive
the totem pole output transistors.

I also DO NOT need 50/50 duty cycle (as I had previously thought).
When I model the load with a signal generator input, I get nearly the
same results as long as the pulse is in the a 2 to 98 percent duty
cycle range.

I have not tried a traingle wave input, but my guess is that it will
work just as well.

What's the easiest method to tune this circuit to operate properly
with 1 or 2 microsecond edges (without wasting additional power)??

Referring to the pdf schematic, there are a couple of things
I'd like you to review.

a) R2 R4 C3 - these are currently sized to produce ~ fixed
3V3 off bias on C3 . C3 charges through the EB jn of Q3
and discharges through R2 (47uSec time constant).
Sustaining conduction current is limited to 33uA by R2.
C3 has little or no effect on Q3 turn-on speed unless a
lot of charge is removed from Q3eb at turn-off (see d).

b) R1 C4 - with a time constant of 10uSec, ~ 2V3 fixed off
bias for Q1 is maintained on C4. A sustaining conduction
base current of 15uA is set by R1 (23uA IQ1 - 7uA IR2).
C4 has little or no effect on turn off speed of Q2, however
when input drive fall time reduces to less than 1usec,
400uA or more will be induced to flow in Q1ec and Q2be for
the duration of the fall time.
This is limited only by the ability of Q1 to produce the
enforced current amplitude; 4mA at 100nS and 40ma at 10nS.
It should not show up as an average increase in current
from V4, however, as total charge is limited by C4 and the
frequency is constant.

c) R5 C2 - with a time constant of 0.5uSec, the current
forced through C2 by drive dV/dt only begins to limit
due to R2 presence when rise/fall times approach 1 uSec,
when turn-on and turn-off currents of 4mA are forced
through either Q2eb or D1. This is an overdrive ratio
of 200:1, based on 15uA sustained conduction base current.
These current amplitudes, by the way, will show up in V4
as Ieb during turn-on of Q2. They will show up in V1 as
ID1 during Q2 turn-off.

d) In saturated switching conditions, bipolar switching speed
depends on base charge removal for turn-off delay calculation.
This makes turn-off longer than turn-on. Without a load in
the circuit, saturation has to be assumed, but because no
collector current is present it's hard to assess what charge
will need to be removed.
If your model includes switching delays, you
may have to introduce a load to get Q2 and Q3 Ice factored in.
Emitter switching and schottky/baker clamping is often used
to reduce turn-off time in higher powered circuits, due to
ce saturation avoidance and controlled eb avalanching.

e) When no collector current is flowing, I think it's safe
to assume that base turn-on overdrive may significantly
increase eb stored charge on subsequent turn-off.

f) When switching totem-pole bipolars, you have to reduce
saturation effects and introduce deadtime to ensure no
cross-conduction occurs. This could be achieved by splitting
up the drive signal, then introducing the appropriate delay
in the drive waveform for upper and lower drive circuits.

g) You have not identified when the cross conduction
current spikes occur - they are likely to show up on
one edge before they show up on the other, due to differing
drive conditions presented by the interface to the local
and floating parts. This may give you some idea on what effect
is occurring first and which delays are dominant.

h) You might also check that, at higher temperatures, the
circuit doesn't heat up without a drive signal. 100K eb
resistors may be too large. You might also consider connecting
R2 to ground, to ensure Q3 is off in the absence of a source.

i) Your circuit must certainly never be driven linearly, by
a sawtooth or triangle waveform. It is not designed for
linear operation.

RL

Only the keyboard has been drinking.

 

[Robert Baer]

If your circuit doesn't need fast edges, and the prblem only occurs
when the input signal dV/dT exceeds a certain value, then filter the
input signal.

Check that the circuit still performs as intended over the
environmental range, though.

What happens to your simulation when the two 105V sources are
connected, or only one is used? You're circuit is unlikely to function
in the real world without very close connection between the emitter of
the upper switch and its associated level-shifting drive circuitry. It
also looks very susceptible to HV supply noise, considering the
capacitive coupling methods used.

RL

Exactly; V1 and V4 should be the *same supply for starters.
My "idea" (not that i created it originally) might still work to pull
stored charge out of the base of Q3.
I see that C3 sort-of does that function, but R4 severely limits the
speed and maybe the total charge removed from the base of Q3.
I would suggest adding a capacitor from the base of Q1 to ground in
the built circuit, near the transistor.

 

[AB]

WOW, you guys are good, thanks.

I have limited time now, but will give some additional information
later tonite.

For now tho...

I've discovered the circuit overdrives by quite a large factor. That
means that it supplies more current to my load than it really has to
in order to make it go. So, some reduction in the peak current
capability is desirable, especially if it reduces the power drawnn
from the 105 v supply.

My load is a 3 stage cockcroft walton supply, current drawn by the
first stage is around 100ua (at 105v), current drawn by the second
stage is 4 ua (at 210v) and current drawn by the third stage is .8 ua
(at 315v).

The caps in the cockcroft Walton are .1 uf, so the totem pole output
has to charge and discharge these caps. In modeling the load
separately, I've found the value of the load resistance has very
little impact on the output and the primary load is from the caps in
the cw multiplier.

I'll publish the complete load later tonight as well.

Thanks so much for all you comments, they help alot. I'm learning so
much from this...both in terms of electronics and in terms of running
the Spice program. Spice is an immensely useful tool which can
supplement the designers talents and save alot of breadboarding
time!!!
!

Regards,

AB

 

[Terry Given]

a) R2 R4 C3 - these are currently sized to produce ~ fixed
3V3 off bias on C3 . C3 charges through the EB jn of Q3
and discharges through R2 (47uSec time constant).
Sustaining conduction current is limited to 33uA by R2.
C3 has little or no effect on Q3 turn-on speed unless a
lot of charge is removed from Q3eb at turn-off (see d).

b) R1 C4 - with a time constant of 10uSec, ~ 2V3 fixed off
bias for Q1 is maintained on C4. A sustaining conduction
base current of 15uA is set by R1 (23uA IQ1 - 7uA IR2).
C4 has little or no effect on turn off speed of Q2, however
when input drive fall time reduces to less than 1usec,
400uA or more will be induced to flow in Q1ec and Q2be for
the duration of the fall time.
This is limited only by the ability of Q1 to produce the
enforced current amplitude; 4mA at 100nS and 40ma at 10nS.
It should not show up as an average increase in current
from V4, however, as total charge is limited by C4 and the
frequency is constant.

c) R5 C2 - with a time constant of 0.5uSec, the current
forced through C2 by drive dV/dt only begins to limit
due to R2 presence when rise/fall times approach 1 uSec,
when turn-on and turn-off currents of 4mA are forced
through either Q2eb or D1. This is an overdrive ratio
of 200:1, based on 15uA sustained conduction base current.
These current amplitudes, by the way, will show up in V4
as Ieb during turn-on of Q2. They will show up in V1 as
ID1 during Q2 turn-off.

d) In saturated switching conditions, bipolar switching speed
depends on base charge removal for turn-off delay calculation.
This makes turn-off longer than turn-on. Without a load in
the circuit, saturation has to be assumed, but because no
collector current is present it's hard to assess what charge
will need to be removed.
If your model includes switching delays, you
may have to introduce a load to get Q2 and Q3 Ice factored in.
Emitter switching and schottky/baker clamping is often used
to reduce turn-off time in higher powered circuits, due to
ce saturation avoidance and controlled eb avalanching.

e) When no collector current is flowing, I think it's safe
to assume that base turn-on overdrive may significantly
increase eb stored charge on subsequent turn-off.

f) When switching totem-pole bipolars, you have to reduce
saturation effects and introduce deadtime to ensure no
cross-conduction occurs. This could be achieved by splitting
up the drive signal, then introducing the appropriate delay
in the drive waveform for upper and lower drive circuits.

g) You have not identified when the cross conduction
current spikes occur - they are likely to show up on
one edge before they show up on the other, due to differing
drive conditions presented by the interface to the local
and floating parts. This may give you some idea on what effect
is occurring first and which delays are dominant.

h) You might also check that, at higher temperatures, the
circuit doesn't heat up without a drive signal. 100K eb
resistors may be too large. You might also consider connecting
R2 to ground, to ensure Q3 is off in the absence of a source.

i) Your circuit must certainly never be driven linearly, by
a sawtooth or triangle waveform. It is not designed for
linear operation.

RL

Only the keyboard has been drinking.

Excellent analysis!

dead time is really the solution - a 74HC14 hex schmitt trigger NOT gate is
the go. Use one NOT gate to buffer the trigger source - the output of the
"buffer" has nicely defined edges. Call this output G1. Pass G1 through a
parallel resistor/diode network (cathode to G1), thence to another NOT gate,
with a cap from anode to 0V 0V. This will give an RC shape to the rising
edge only. The output of this NOT gate will thus be a squarewave, with the
rising edge edge delayed - call it G2.

Pass G1 throu another NOT gate, generating G3 (simply inverted version of
G1). Use another identical RCD-NOT network to generate G4. G2 & G4 are now
non-overlapping square waves with well defined rise/fall times. Fiddle with
R,C to adjust the dead time. Keep R > 400R to minimise peak current required
from NOT gate; keep C > 47pF to swamp input capacitance of gate, ensuring
reliable operation.

In general capacitive speed-up does not work too well with high-voltage
bipolars, but the MPSA42/92 pair should be OK. Spice does not always tell
the truth though, and it wont point things out - you have to go looking. The
Ebers-Moll transistor model does NOT model B-E reverse breakdown (I've been
bitten by this).

One thing missing from your circuit is fast diodes across the 2 switching
transistors - cathodes UP. When you drive an inductive load (and you will)
the current has to go somewhere when one device switches - without these
diodes, the circuit will destroy itself the instant you try to run an
inductive load. something like a BYV26 would eat it - only need 150V rating
for 105Vdc supply, but 200V would do fine. They should be FAST - 25ns or so
Trr (reverse-recovery time, how fast diode stops conducting when reverse
biased). DONT use 1N400x diodes - they are SLOW, around 1us Trr.

Try splitting the 105Vdc power supply in two, and connecting a 1mH inductor
+ 10R resistor from the chopper output to the mid-point of the dc bus, and
see what happens. The voltage spike will of course be L*dI/dt where dI is
the current in the transistor/inductor when the tranny is switched OFF, and
dt is the switching time. This is what destroys semiconductors in power
electronic circuits.....then change the resistor to 1k, and no inductor -
voila, voltage spikes gone.

 

[AB]

OK, thanks all. I had the day from Hell yesterday and there is more of
the same today. Sorry I can't reply as well as I'd like to.

It's clear that I am overdriving to some extent and I could probably
tune it down some.

But, my load is a cockcroft-walton voltage multiplier consisting of .1
uf caps that have to be charged and discharged and it takes fairly
hefty current to do it.

I've posted the diagram of the worst case and minimum/typical load
schematic diagrams on my personal web space. Bear in mind that each
stage of the cw is loaded to some degree and the load resistors show
the load for each stage under worst case/minimum/typical case.

http://www.uninets.net/~artky1k/max_min.PDF

In reality there are 10 stages in the cw, I've simplified it by only
using 3 stages. This is probably ok becasue the resistive loads for
the upper stages are pico and nano amps. Not sure whether I have to
account for the additional diodes in the upper stages tho (even though
there is practically no current being drawn.

More later.

Thanks to all for comments and suggestions.

AB

 

[AB]

OK, I did some further testing this morning.

I set the signal generator for 100 ns rise and fall times.

I broke up the circuit such that each output transistor had a 1 ma
collector resistor (100K) and fed each transistor had it's own 105 v
power supply.

The result is that each transistor has it's own power supply and it's
own collector resistor. I can look at the switching of each transistor
separately now.

The results were pretty sobering!!!!!!!!!!!!!!!!!!

I zoomed in on the high to low transition of the signal generator and
marked this transition period.

Switching to the collector of Q2, I can see it starts to change about
50 us after the input signal starts to change (it's delayed by 50 us).
It is done with it's transition about 75 us later.

Looking that the collector of Q2 is a different story however! It
takes 1.3 us to change from completely on to completely off and it
does not even start to change for 200 ns! So, there is 100 ns where
both transistors are fully conducting and an additional 1.1 us overlap
when both transistors are partially on.

No wonder I'm getting the big spikes power supply spikes at the H>L
transistion of the signal generator!

Not sure what to do about it, but I can see the problem now, Spice
simulation is good!!!!!

Not sure whether to delay the timing of the input signal feeding Q2
(as one of you suggested) or whether I should try to speed up the Q2
switching time by pulling the base down harder (as another user
suggested).

Again, I thank you all. Further suggections are very much appreciated.

AB

 

[R.Legg]

OK, I did some further testing this morning.

I set the signal generator for 100 ns rise and fall times.

I broke up the circuit such that each output transistor had a 1 ma
collector resistor (100K) and fed each transistor had it's own 105 v
power supply.

The result is that each transistor has it's own power supply and it's
own collector resistor. I can look at the switching of each transistor
separately now.

Switching to the collector of Q2, I can see it starts to change about
50 us after the input signal starts to change (it's delayed by 50 us).
It is done with it's transition about 75 us later.

You mean nSec.

Your switching period is only 50uSec on each arm, at 10KHz.

No wonder I'm getting the big spikes power supply spikes at the H>L
transistion of the signal generator!

Not sure what to do about it, but I can see the problem now, Spice
simulation is good!!!!!

Not sure whether to delay the timing of the input signal feeding Q2
(as one of you suggested) or whether I should try to speed up the Q2
switching time by pulling the base down harder (as another user
suggested).

If your load was inductive, you could let it handle the transitions.

Where is your 105V supposed to come from in the first place?

RL

 

[AB]

You mean nSec.

Yes, correct, my error. Should have said nSec.

If your load was inductive, you could let it handle the transitions.

OK, it's capacitive and there should be very little inductance. I did
post the schematic of the intended load, see previous message.

Where is your 105V supposed to come from in the first place?

My hope is that I will get ~100v by series connecting 9 v battteries
or by having a stack of small 3 volt rechargable batteries in series.
To do it, I need very minimal current draw from the switching
circuit...hence my interest in optimization of the driver circuit.

I have also just learned of a developer of micro sized rechargable
batteries using MEMS technology. If the batteries can be made small
enough, I could mount them in series on a small pcb, one set for each
dynode. This would be most direct and wouldn't require any switching
at all!

I'm also interested in piezotransformers and might try to generate 100
volts using those little gems.

I spent a good part of the day today in various doctors offices in the
'hurry up and wait mode'. Before I left for the day, I printed out the
schematic and all the comments sent by usenet readers. I spent lots of
time reading them and making notes.

It appears I need an NPN transistor that will withstand 125 Vce and
one that has smaller Ccb than the MPSA42 transistor that I'm using for
Q3. Not sure if such a beast exists, the A42 has been around for a
long time and they're still makin' em! The most direct fix is to find
a more appropriate transistor, anyone have any suggestions?? I've
looked at Zetex, but they don't seem to be into higher voltage
ratings:>:

Thanks,

AB