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!00 Mhz sine to (TTL or lock signal) translator Device?

Discussion in 'Electronic Components' started by LOC, Oct 21, 2004.

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  1. LOC

    LOC Guest

    Hi all,
    I am looking for a device to translate 100Mhz sineusoidal waveform, -
    2 dBm, load 50 ohm (it meams 0.5V peak to peak, DC offset 0 Volt) to
    TTL level. The supply is -/+5 Volt. I know using a comparator can do
    the work, but it is not fast device for 100Mhz to TTL. Please help,
    what device or any way recommended will be appreciated.
    Loc
     
  2. LOC wrote...
    What are you going to drive with the resulting "TTL" signal?
     
  3. Hal Murray

    Hal Murray Guest

    I am looking for a device to translate 100Mhz sineusoidal waveform, -
    Do you want a one-shot solution, or a cheap but rock solid
    design for a huge production run?

    100 MHz isn't all that fast for modern logic.

    My first try would be a high speed CMOS inverter. TI has
    several families. So do many other vendors.

    Couple your signal in through a cap and bias the input
    through a 1 meg (or 100K) resistor from the output. I
    don't know if 1/2 V p-p is enough. Going through another
    gate might help to clean it up.

    You could also try using a ECL/PECL to TTL converter chip.
    1/2 V would be plenty of swing for that.

    They do make fast comparators. Most of them have ECL outputs.
    It's probably worth a scan through various manufacturers
    web sites. TI, National, Linear Technology, Maxim, ...
     
  4. LOC

    LOC Guest

    Output signal will drive CPLD (requires minimum High i/p Voltage = 2V,
    Max Low i/p V =0.8 V) 3.3 V supply
     
  5. LOC

    LOC Guest

    You are right. they are fast today. I looked at my old data book, ECL
    to TTL delay 9.6ns from High to Low. Now is max 6.2 ns delay for High
    to Low or (Low to High). min 1.6 ns delay for Low to High. It is o.k
    1/2V is not good for Input Level requirement of ECL side
    Anyway, thanks for advice.
     
  6. LOC wrote...
    There are fast expensive comparators, but that does seem overkill.

    Hal suggested cap coupling your signal to an inverter stage and
    biasing the inverter from its output with a 100k resistor. This
    is a simple approach and works well up to say 50MHz with ordinary
    HC logic inverters (the unbuffered types are preferred), but it's
    likely to be marginal at 100MHz.

    Your cPLD's logic gates are fast enough, and I have successfully
    used cPLD inputs in a linear manner (e.g. for crude timers), but
    one wouldn't suggest using the class-A biasing trick with a cPLD.

    So your best bet may be one of the newer faster logic families.
    For example, TI's 74AHCU04 has a typical 3.5ns propagation delay
    into a 15pF load, operated from 5V, so it's clearly fast enough
    to work fine with a 5ns high and 5ns low square wave. ON Semi's
    74VHC1GU04DT single gate inverter is rated at 2.5ns typical.

    Note how the smaller part (the 1GU04DT comes in a sot23 package)
    follows the established rule of having a longer part number.
     
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