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0.13µm CMOS

Discussion in 'Electrical Engineering' started by Geronimo Stempovski, May 11, 2007.

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  1. Hi all,

    currently I am investigating a data sorting algorithm on hardware. The
    algorithm was implemented in VHDL and is currently running on a Xilinx
    Virtex-II Pro XC2VP70 - FF1704 FPGA. Power consumption is a crucial aspect
    in the target application. Therefore I made an analysis with the Xilinx
    Virtex-II Pro Web Power Tool (www.xilinx.com) and obtained satisfying
    results.

    Now I'd like to make an estimation what this circuit would consume on a
    comparable ASIC 0.13µm CMOS technology (the FPGA is also based on a 0.13µm
    CMOS technology). The target clock frequency is 180 MHz, activity ratio is
    15%. Is there any rule of thumb or calculation rule?

    Any help is highly appreciated !!!!

    Regards Gero
     
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