Connect with us

Going digital

Digital simulation in LTSPICE

  1. Harald Kapp
    A word in advance: SPICE is not a digital simulator. There are much better specialized tools out there for this purpose.

    Having said that, LTSPICE does have limited digital simulation capabilities. They are provided for those cases where a mixed mode simulation (analog + digital) cannot be avoided. Since the use of digital logic in LTSPICE is not self-explanatory, here are some tips to get you started:

    figure 1.png
    Figure 1 basic AND gate

    Figure 1 shows a basic AND gate( other types of gate are available, see LTSPICE help). The gate has 5 inputs (1...5) to the left, one common return pin (8) at the bottom plus 2 outputs, one inverting, the other non-inverting (note that the pin numbers are not shown on the LTSPICE schematic - I have put them manually into figure 1 for explanation only). Thus the gate may be used either as an AND gate or as a NAND gate. Use the gate as follows (cf. figure 2):
    • Any unused input and/or output has to be connected to pin 8 (LTSPICE will recognize that these I/Os are unused and remove them from the simulation).
    • Pin 8 (plus the unused I/Os) has to be connected to the common ground of the circuit.
    • The used output needs a path to ground, so you have to connect at least a resistor to ground. Otherwise LTSPICE will throw an error.
    • There is no power supply for the logic gates (other than the common return pin 8).
    figure 2.png Figure 2 complete NAND circuit

    Note that I added a fixed voltage to each trace in figure 2. Thus the traces are stacked on top of each other to better distinguish between the different traces. A good offset is n*(Vcc+0.5 V) for traces 1...max (assuming the bottom trace is trace 0). In figure 2 Vcc=1 V (see below), thus the offsets are 0 V (trace 0), 1.5 V (trace 1) and 3 V (trace 2).

    In addition it has to be noted that the LTSPICE logic gates by default operate with 0V...1V logic levels and a threshold of 0.5 V:
    • U <0.5 V -> logic low
    • U >0.5 V -> logic high
    Thus level shifting may be required in real circuits to adapt the LTSPICE models to the voltage level of the surrounding circuit. Alternatively the output voltages for logic High (and logic Low, although this is in my opinion not very useful) as well as the threshold voltage may be set using attributes of the logic gate.

    Figure 3 shows the attribute dialog (in LTSPICE: right click on the symbol to open the dialog) for the NAND gate of figure 2 where the output voltage for logic High is set to 5 V and the threshold is set to 2.5 V (if you do not set the threshold manually, it is calculated as 1/2*(Vhigh+Vlow).

    figure 3.png
    Figure 3 Attributes of the NAND gate

    Other parameters may be set as well (from the TLSPICE help):
    figure 4.png

    The propagation delay of an LTSPICE logic gate defaults to 0 ns and has to be set to a meaningful value using the parameter td in the attribute dialog (figure 3).

    SPICE help topics to look at: Special functions

    Harald Kapp, 2014-05-13
Electronics Point Logo
Continue to site
Quote of the day

-